[coreboot-gerrit] Patch set updated for coreboot: google/gru: Add USB 2.0 PHY tuning for Kevin
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Sun Aug 21 04:15:57 CEST 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16265
-gerrit
commit 7ea67b85fe321cef73fee82aa896ba5cd32b7c55
Author: Julius Werner <jwerner at chromium.org>
Date: Mon Aug 15 17:58:05 2016 -0700
google/gru: Add USB 2.0 PHY tuning for Kevin
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth at chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck at chromium.org>
Original-Reviewed-by: David Schneider <dnschneid at chromium.org>
---
src/mainboard/google/gru/mainboard.c | 13 +++++++++++++
src/soc/rockchip/rk3399/include/soc/grf.h | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 8a6cda2..7fd8f14 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -158,6 +158,19 @@ static void configure_display(void)
static void setup_usb(void)
{
+ /*
+ * A few magic PHY tuning values that improve eye diagram amplitude
+ * and make it extra sure we get reliable communication in firmware.
+ */
+
+ /* Set max ODT compensation voltage and current tuning reference. */
+ write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3);
+ write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3);
+
+ /* Set max pre-emphasis level, only on Kevin PHY0. */
+ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
+ write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7);
+
setup_usb_otg0();
setup_usb_otg1();
}
diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h
index d76b827..c1fd690 100644
--- a/src/soc/rockchip/rk3399/include/soc/grf.h
+++ b/src/soc/rockchip/rk3399/include/soc/grf.h
@@ -73,7 +73,7 @@ struct rk3399_grf_regs {
u32 reserved11[3];
u32 usbphy0_ctrl[26];
u32 reserved12[6];
- u32 usbphy1[26];
+ u32 usbphy1_ctrl[26];
u32 reserved13[0x72f];
u32 soc_con9;
u32 reserved14[0x0a];
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