[coreboot-gerrit] New patch to review for coreboot: intel/amenia: Update EMMC DLL settings

[Bora Guvendik (bora.guvendik@intel.com)]

Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16237

-gerrit

commit 637398fb48af5c4f132c119698b29fbc64411276
Author: Bora Guvendik <bora.guvendik at intel.com>
Date:   Tue Aug 16 14:43:16 2016 -0700

    intel/amenia: Update EMMC DLL settings
    
    Update EMMC DLL setting for amenia board, after that system can
    boot up with EMMC successfully.
    
    BUG=chrome-os-partner:51844
    TEST=Boot up with EMMC
    
    Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef
    Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
 src/mainboard/intel/amenia/devicetree.cb | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index 4b620a0..80fc29c 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -12,6 +12,26 @@ chip soc/intel/apollolake
 	# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
 	register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
 
+	# EMMC TX DATA Delay 2#
+	# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
+	# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
+	# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
+	# 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode
+	register "emmc_tx_data_cntl2" = "0x1c1c1c00"
+
+	# EMMC RX CMD/DATA Delay 1#
+	# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
+	# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
+	# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
+	# 0x00[6:0] stands for 0 delay for SDR12/Compatibility
+	register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00"
+
+	# EMMC RX CMD/DATA Delay 2#
+	# 0x01[17:16] stands for Rx Clock before Output Buffer
+	# 0x00[14:8] stands for 0 delay for Auto Tuning Mode
+	# 0x1C[6:0] stands for 28*125 =  3500 pSec delay for SDR104/HS200
+	register "emmc_rx_cmd_data_cntl2" = "0x1001c"
+
 	# LPSS S0ix Enable
 	register "lpss_s0ix_enable" = "1"