[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Remove UPD parameters

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14451

-gerrit

commit ebda0bff7b5ad1f6b7a4f0193877413c18d3bc67
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Fri Mar 11 07:55:24 2016 -0800

    soc/intel/quark: Remove UPD parameters
    
    Remove the UPD parameters to match QuarkFsp code at
    https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp
    
    TEST=Build and run on Galileo Gen2
    
    Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
 src/soc/intel/quark/chip.c              |  4 ++--
 src/soc/intel/quark/romstage/romstage.c | 15 ++-------------
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index eb326d7..afc1244 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -55,7 +55,7 @@ struct chip_operations soc_intel_quark_ops = {
 	.enable_dev	= chip_enable_dev,
 };
 
-void soc_silicon_init_params(SILICON_INIT_UPD *params)
+void soc_silicon_init_params(SILICON_INIT_UPD *upd)
 {
 	struct soc_intel_quark_config *config;
 	device_t dev;
@@ -79,5 +79,5 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	SILICON_INIT_UPD *new)
 {
 	/* Display the parameters for SiliconInit */
-//	printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+	printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
 }
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 5bedb25..fb91c58 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -82,11 +82,7 @@ void soc_memory_init_params(struct romstage_params *params,
 	config = dev->chip_info;
 
 	/* Set the parameters for MemoryInit */
-	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
-	upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
-		config->PcdSmmTsegSize : 0;
-	upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file;
-	upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len;
+//	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
 
 	/* Display the ROM shadow data */
 	hexdump((void *)0x000ffff0, 0x10);
@@ -117,12 +113,5 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	MEMORY_INIT_UPD *new)
 {
 	/* Display the parameters for MemoryInit */
-	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
-	fsp_display_upd_value("PcdSmmTsegSize", 2,
-		old->PcdSmmTsegSize, new->PcdSmmTsegSize);
-	fsp_display_upd_value("PcdPlatformDataBaseAddress", 4,
-		old->PcdPlatformDataBaseAddress,
-		new->PcdPlatformDataBaseAddress);
-	fsp_display_upd_value("PcdPlatformDataMaxLen", 4,
-		old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen);
+//	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
 }