[coreboot-gerrit] New patch to review for coreboot: google/gru: Incorporate feedback to #14279
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Apr 14 14:48:26 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14362
-gerrit
commit 95361d1e81f4582ee413a722c4583f4524270619
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Thu Apr 14 14:45:22 2016 +0200
google/gru: Incorporate feedback to #14279
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:
- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
per-board copy pasta)
Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
src/mainboard/google/gru/Kconfig | 1 +
src/mainboard/google/gru/Makefile.inc | 1 -
src/mainboard/google/gru/chromeos.c | 4 ----
src/mainboard/google/gru/chromeos.fmd | 2 +-
src/mainboard/google/gru/mainboard.c | 5 -----
src/mainboard/google/gru/romstage.c | 34 ----------------------------------
src/soc/rockchip/rk3399/Makefile.inc | 1 +
src/soc/rockchip/rk3399/romstage.c | 34 ++++++++++++++++++++++++++++++++++
8 files changed, 37 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index c225d10..6f234ad 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -41,6 +41,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
+ default "Kevin" if BOARD_GOOGLE_KEVIN
default "Gru"
config MAINBOARD_VENDOR
diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc
index 752830c..879520c 100644
--- a/src/mainboard/google/gru/Makefile.inc
+++ b/src/mainboard/google/gru/Makefile.inc
@@ -29,7 +29,6 @@ romstage-y += boardid.c
romstage-y += chromeos.c
romstage-y += memlayout.ld
romstage-y += reset.c
-romstage-y += romstage.c
ramstage-y += boardid.c
ramstage-y += chromeos.c
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index 6f9380d..da57d86 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -15,10 +15,6 @@
*/
#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd
index c381170..bf30ddf 100644
--- a/src/mainboard/google/gru/chromeos.fmd
+++ b/src/mainboard/google/gru/chromeos.fmd
@@ -25,5 +25,5 @@ FLASH at 0x0 0x800000 {
SHARED_DATA at 0x0 0x10000
}
RW_NVRAM at 0x5f0000 0x10000
- RW_LEGACY at 0x600000 0x200000
+ RW_LEGACY(CBFS)@0x600000 0x200000
}
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 1641838..649f162 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -14,12 +14,7 @@
*
*/
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boardid.h>
-#include <boot/coreboot_tables.h>
#include <device/device.h>
-#include <console/console.h>
static void mainboard_init(device_t dev)
{
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
deleted file mode 100644
index 4786937..0000000
--- a/src/mainboard/google/gru/romstage.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-#include <symbols.h>
-
-void main(void)
-{
- console_init();
- exception_init();
- cbmem_initialize_empty();
- run_ramstage();
-}
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 54a7b51..957124e 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -38,6 +38,7 @@ romstage-y += ../common/spi.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += clock.c
romstage-y += timer.c
+romstage-y += romstage.c
################################################################################
diff --git a/src/soc/rockchip/rk3399/romstage.c b/src/soc/rockchip/rk3399/romstage.c
new file mode 100644
index 0000000..4786937
--- /dev/null
+++ b/src/soc/rockchip/rk3399/romstage.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <arch/cache.h>
+#include <arch/cpu.h>
+#include <arch/exception.h>
+#include <arch/io.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <romstage_handoff.h>
+#include <symbols.h>
+
+void main(void)
+{
+ console_init();
+ exception_init();
+ cbmem_initialize_empty();
+ run_ramstage();
+}
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