[coreboot-gerrit] New patch to review for coreboot: northbridge/amd/{lx, gx2}: remove immediate accesses of 0

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14345

-gerrit

commit 74a74f18fc541d49db9638bb06dfb6668515dee0
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Apr 13 21:00:12 2016 +0200

    northbridge/amd/{lx,gx2}: remove immediate accesses of 0
    
    gcc doesn't like these because they're undefined behavior, so use
    zeroptr instead. For the loop that just does a number of writes (0..4),
    use zeroptr + i.
    
    Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
    ud2 anymore and to look reasonable where zeroptr was used.
    
    Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/northbridge/amd/gx2/northbridgeinit.c | 2 +-
 src/northbridge/amd/gx2/raminit.c         | 5 ++---
 src/northbridge/amd/lx/northbridgeinit.c  | 2 +-
 src/northbridge/amd/lx/raminit.c          | 5 ++---
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 319d95a..348cdb9 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -656,7 +656,7 @@ void northbridge_init_early(void)
 
 	/* Now that the descriptor to memory is set up. */
 	/* The memory controller needs one read to synch its lines before it can be used. */
-	i = *(volatile int *) 0;
+	read32(zeroptr);
 
 	GeodeLinkPriority();
 
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 46ec6b8..db10138 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -16,6 +16,7 @@
 
 #include <cpu/amd/gx2def.h>
 #include <spd.h>
+#include <stddef.h>
 
 static const unsigned char NumColAddr[] = {
 	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
@@ -596,10 +597,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	/* The RAM dll needs a write to lock on so generate a few dummy writes */
 	/* Note: The descriptor needs to be enabled to point at memory */
-	volatile unsigned long *ptr;
 	for (i = 0; i < 5; i++) {
-		ptr = (void *)i;
-		*ptr = (unsigned long)i;
+		write32(zeroptr + i, i);
 	}
 
 	printk(BIOS_INFO, "RAM DLL lock\n");
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index a07a1ea..f385770 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -738,7 +738,7 @@ void northbridge_init_early(void)
 
 	/*  Now that the descriptor to memory is set up. */
 	/*  The memory controller needs one read to synch its lines before it can be used. */
-	i = *(volatile int *)0;
+	read32(zeroptr);
 
 	GeodeLinkPriority();
 
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index f20aed2..c540f9a 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -18,6 +18,7 @@
 #include <cpu/amd/lxdef.h>
 #include <arch/io.h>
 #include <spd.h>
+#include <stddef.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "raminit.h"
 #include "northbridge.h"
@@ -747,10 +748,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	/* The RAM dll needs a write to lock on so generate a few dummy writes */
 	/* Note: The descriptor needs to be enabled to point at memory */
-	volatile unsigned long *ptr;
 	for (i = 0; i < 5; i++) {
-		ptr = (void *)i;
-		*ptr = (unsigned long)i;
+		write32(zeroptr + i, i);
 	}
 	/* SWAPSiF for PBZ 4112 (Errata 34) */
 	/* check for failed DLL settings now that we have done a memory write. */