[coreboot-gerrit] New patch to review for coreboot: src/soc/intel/common: Fix CID 1295499, remove dead code
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue Apr 12 22:24:27 CEST 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14337
-gerrit
commit 2456c49414848decfaea911d5adc41a760d75fa1
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Tue Apr 12 13:01:02 2016 -0700
src/soc/intel/common: Fix CID 1295499, remove dead code
Restructure the nvm_is_write_protected routine to eliminate the dead
code error.
TEST=Build and run on Kunimitsu
Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/common/nvm.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index e55638a..003a6ca 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -96,17 +96,13 @@ int nvm_write(void *start, const void *data, size_t size)
/* Read flash status register to determine if write protect is active */
int nvm_is_write_protected(void)
{
- u8 sr1;
- u8 wp_gpio = 0;
- u8 wp_spi;
-
if (nvm_init() < 0)
return -1;
#if IS_ENABLED(CONFIG_CHROMEOS)
- /* Read Write Protect GPIO if available */
- wp_gpio = get_write_protect_state();
-#endif
+ u8 sr1;
+ u8 wp_gpio;
+ u8 wp_spi;
/* Read Status Register 1 */
if (flash->status(flash, &sr1) < 0) {
@@ -114,11 +110,16 @@ int nvm_is_write_protected(void)
return -1;
}
wp_spi = !!(sr1 & 0x80);
+ printk(BIOS_DEBUG, "SPI flash SRP0=%d\n", wp_spi);
- printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n",
- wp_gpio, wp_spi);
-
- return wp_gpio && wp_spi;
+ if (wp_spi) {
+ /* Read Write Protect GPIO if available */
+ wp_gpio = get_write_protect_state();
+ printk(BIOS_DEBUG, "SPI flash WPSW=%d\n", wp_gpio);
+ return wp_gpio;
+ }
+#endif
+ return false;
}
/* Apply protection to a range of flash */
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