[coreboot-gerrit] New patch to review for coreboot: google/glados: Set the type-c flex port to max USB2 settings

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12204

-gerrit

commit e3b5e14e52b67767e9a5545ba5ec197444f70b1f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Oct 26 15:28:59 2015 -0700

    google/glados: Set the type-c flex port to max USB2 settings
    
    Change the tuning setting for the type-c port that is over
    the flex cable to use the max possible drive strength.
    
    Also fix up the comments to indicate what Type-c port goes
    where instead of just referring to them by number.
    
    BUG=chrome-os-partner:45367
    BRANCH=none
    TEST=build and boot on glados
    
    Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d
    Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/309010
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index a9e816c..7e1e6c7 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -53,15 +53,15 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[0]" = "1"
 	register "PcieRpClkReqNumber[4]" = "2"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port (board)
+	register "usb2_ports[1]" = "USB2_PORT_MAX"     # Type-C Port (flex)
 	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
 	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port 1
 	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
 	register "usb2_ports[8]" = "USB2_PORT_MID"     # Type-A Port 2
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port (board)
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port (flex)
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2