[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 952cb03b9e08883da46fb57f99aec919f5a9b60a
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Mon Oct 5 19:11:39 2015 +0530

    intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
    
    In FSP 1.7.0 SataMode and SataEnable have been moved from
    MemoryInit to SiliconInit. Also, GpioTablePtr has been removed.
    
    USB phy settings added to SiliconInit, Enable the configs for USB
    equalization settings in coreboot.
    
    Addition of serialIO UPD to indicate FSP not to reinitialise
    UART2 controller during MemoryInit.
    
    BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374
    TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC,
    	USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume
    
    CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949
    
    Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73
    Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/303661
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/12144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/12144 for details.

-gerrit