[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Clean up USB configuration in devicetree
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Oct 23 13:26:12 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12163
-gerrit
commit 81fb33e282f55059e2495d401ceb6605f258e6ed
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Fri Oct 16 13:58:11 2015 -0700
intel/skylake: Clean up USB configuration in devicetree
Instead of having many different arrays for USB configuration,
with each array containing one bit of information, have one
array containing all the information for each port.
This way we can put the basic tuning parameters into a
structure and then define structures for the basic supported
configurations.
The existing port definitions are taken from the Skylake HSIO
tuning guide.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados, verify USB functionality in
all ports.
Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506
Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/306734
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/chell/devicetree.cb | 59 ++--------
src/mainboard/google/glados/devicetree.cb | 61 ++--------
src/mainboard/intel/kunimitsu/devicetree.cb | 38 ++-----
src/soc/intel/skylake/chip.c | 45 ++++----
src/soc/intel/skylake/chip.h | 13 +--
src/soc/intel/skylake/include/soc/usb.h | 167 ++++++++++++++++++++++++++++
6 files changed, 228 insertions(+), 155 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 5701daf..dfa588a 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -53,54 +53,17 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
- register "PortUsb20Enable[0]" = "1" # Type-C Port 1
- register "PortUsb20Enable[1]" = "1" # Type-A Port
- register "PortUsb20Enable[2]" = "1" # Camera
- register "PortUsb20Enable[3]" = "1" # Bluetooth
- register "PortUsb20Enable[4]" = "1" # SD
- register "PortUsb20Enable[5]" = "1" # Type-C Port 2
-
- register "PortUsb30Enable[0]" = "1" # Type-C Port 1
- register "PortUsb30Enable[1]" = "1" # Type-C Port 2
- register "PortUsb30Enable[2]" = "1" # Type-A Port
- register "PortUsb30Enable[3]" = "1" # SD
-
- # USB Per Port HS Preemphasis Bias
- register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
- 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
- 0x07, 0x07, 0x07, 0x07 }"
-
- # USB Per Port HS Transmitter Bias
- register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00 }"
-
- # USB Per Port HS Transmitter Emphasis
- register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
- 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \
- 0x03, 0x03, 0x03, 0x03 }"
-
- # USB Per Port Half Bit Pre-emphasis
- register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
- 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00 }"
-
- # Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
- # USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
- # Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00 }"
-
- # USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_MID" # Type-A Port
+ register "usb2_ports[2]" = "USB2_PORT_FLEX" # Camera
+ register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MID" # SD
+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 797865d..a9e816c 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -53,54 +53,17 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
- register "PortUsb20Enable[0]" = "1" # Type-C Port 1
- register "PortUsb20Enable[1]" = "1" # Type-C Port 2
- register "PortUsb20Enable[2]" = "1" # Bluetooth
- register "PortUsb20Enable[4]" = "1" # Type-A Port 1
- register "PortUsb20Enable[6]" = "1" # Camera
- register "PortUsb20Enable[8]" = "1" # Type-A Port 2
-
- register "PortUsb30Enable[0]" = "1" # Type-C Port 1
- register "PortUsb30Enable[1]" = "1" # Type-C Port 2
- register "PortUsb30Enable[2]" = "1" # Type-A Port 1
- register "PortUsb30Enable[3]" = "1" # Type-A Port 2
-
- # USB Per Port HS Preemphasis Bias
- register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
- 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
- 0x07, 0x07, 0x07, 0x07 }"
-
- # USB Per Port HS Transmitter Bias
- register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00 }"
-
- # USB Per Port HS Transmitter Emphasis
- register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
- 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \
- 0x03, 0x03, 0x03, 0x03 }"
-
- # USB Per Port Half Bit Pre-emphasis
- register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
- 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00 }"
-
- # Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
- # USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
- # Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00 }"
-
- # USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
- 0x00, 0x00, 0x00, 0x00, 0x00 }"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+ register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port 1
+ register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_MID" # Type-A Port 2
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
@@ -114,7 +77,7 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
device cpu_cluster 0 on
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index dfba699..e377a51 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -53,35 +53,17 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
- register "PortUsb20Enable[0]" = "1" # Type-C Port 1
- register "PortUsb20Enable[1]" = "1" # Type-C Port 2
- register "PortUsb20Enable[2]" = "1" # Bluetooth
- register "PortUsb20Enable[4]" = "1" # Type-A Port (card)
- register "PortUsb20Enable[6]" = "1" # Camera
- register "PortUsb20Enable[8]" = "1" # Type-A Port (board)
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+ register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card)
+ register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board)
- #USB Per Port HS Preemphasis Bias
- register "Usb2AfePetxiset" = "{0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}"
- #USB Per Port HS Transmitter Bias
- register "Usb2AfeTxiset" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
- #USB Per Port HS Transmitter Emphasis
- register "Usb2AfePredeemp" = "{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}"
- #USB Per Port Half Bit Pre-emphasis
- register "Usb2AfePehalfbit" = "{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
-
- register "PortUsb30Enable[0]" = "1" # Type-C Port 1
- register "PortUsb30Enable[1]" = "1" # Type-C Port 2
- register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
- register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
-
- #Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- register "Usb3HsioTxDeEmphEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
- #USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- register "Usb3HsioTxDeEmph" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
- #Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmpEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
- #USB 3.0 TX Output Downscale Amplitude Adjustment
- register "Usb3HsioTxDownscaleAmp" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2613d38..44f247f 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -275,28 +275,33 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
- memcpy(params->PortUsb20Enable, config->PortUsb20Enable,
- sizeof(params->PortUsb20Enable));
- memcpy(params->PortUsb30Enable, config->PortUsb30Enable,
- sizeof(params->PortUsb30Enable));
- memcpy(params->Usb2AfePetxiset, config->Usb2AfePetxiset,
- sizeof(params->Usb2AfePetxiset));
- memcpy(params->Usb2AfeTxiset, config->Usb2AfeTxiset,
- sizeof(params->Usb2AfeTxiset));
- memcpy(params->Usb2AfePredeemp, config->Usb2AfePredeemp,
- sizeof(params->Usb2AfePredeemp));
- memcpy(params->Usb2AfePehalfbit, config->Usb2AfePehalfbit,
- sizeof(params->Usb2AfePehalfbit));
+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+ params->PortUsb20Enable[i] =
+ config->usb2_ports[i].enable;
+ params->Usb2AfePetxiset[i] =
+ config->usb2_ports[i].pre_emp_bias;
+ params->Usb2AfeTxiset[i] =
+ config->usb2_ports[i].tx_bias;
+ params->Usb2AfePredeemp[i] =
+ config->usb2_ports[i].tx_emp_enable;
+ params->Usb2AfePehalfbit[i] =
+ config->usb2_ports[i].pre_emp_bit;
+ }
- memcpy(params->Usb3HsioTxDeEmphEnable, config->Usb3HsioTxDeEmphEnable,
- sizeof(params->Usb3HsioTxDeEmphEnable));
- memcpy(params->Usb3HsioTxDeEmph, config->Usb3HsioTxDeEmph,
- sizeof(params->Usb3HsioTxDeEmph));
- memcpy(params->Usb3HsioTxDownscaleAmpEnable, config->Usb3HsioTxDownscaleAmpEnable,
- sizeof(params->Usb3HsioTxDownscaleAmpEnable));
- memcpy(params->Usb3HsioTxDownscaleAmp, config->Usb3HsioTxDownscaleAmp,
- sizeof(params->Usb3HsioTxDownscaleAmp));
+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ if (config->usb3_ports[i].tx_de_emp) {
+ params->Usb3HsioTxDeEmphEnable[i] = 1;
+ params->Usb3HsioTxDeEmph[i] =
+ config->usb3_ports[i].tx_de_emp;
+ }
+ if (config->usb3_ports[i].tx_downscale_amp) {
+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ params->Usb3HsioTxDownscaleAmp[i] =
+ config->usb3_ports[i].tx_downscale_amp;
+ }
+ }
params->SataSalpSupport = config->SataSalpSupport;
params->SataPortsEnable[0] = config->SataPortsEnable[0];
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b54869c..c093d91 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -28,6 +28,7 @@
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
+#include <soc/usb.h>
struct soc_intel_skylake_config {
/*
@@ -162,18 +163,10 @@ struct soc_intel_skylake_config {
u8 PcieRpClkReqNumber[20];
/* USB related */
- u8 PortUsb20Enable[16];
- u8 PortUsb30Enable[10];
+ struct usb2_port_config usb2_ports[16];
+ struct usb3_port_config usb3_ports[10];
u8 XdciEnable;
u8 SsicPortEnable;
- u8 Usb2AfePetxiset[16];
- u8 Usb2AfeTxiset[16];
- u8 Usb2AfePredeemp[16];
- u8 Usb2AfePehalfbit[16];
- u8 Usb3HsioTxDeEmphEnable[10];
- u8 Usb3HsioTxDeEmph[10];
- u8 Usb3HsioTxDownscaleAmpEnable[10];
- u8 Usb3HsioTxDownscaleAmp[10];
/* SMBus */
u8 SmbusEnable;
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
new file mode 100644
index 0000000..29b603a
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+#define USB2_EMP_OFF 0
+#define USB2_DE_EMP_ON 1
+#define USB2_PRE_EMP_ON 2
+
+#define USB2_FULL_BIT_PRE_EMP 0
+#define USB2_HALF_BIT_PRE_EMP 1
+
+#define USB2_BIAS_0MV 0
+#define USB2_BIAS_11MV 1
+#define USB2_BIAS_17MV 2
+#define USB2_BIAS_28MV 3
+#define USB2_BIAS_28MV2 4
+#define USB2_BIAS_39MV 5
+#define USB2_BIAS_45MV 6
+#define USB2_BIAS_56MV 7
+
+struct usb2_port_config {
+ uint8_t enable;
+ uint8_t tx_bias;
+ uint8_t tx_emp_enable;
+ uint8_t pre_emp_bias;
+ uint8_t pre_emp_bit;
+};
+
+#define USB2_PORT_EMPTY { \
+ .enable = 0, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_EMP_OFF, \
+ .pre_emp_bias = USB2_BIAS_0MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/*
+ * Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down
+ */
+
+/* 11.5"-12" */
+#define USB2_PORT_LONG { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_39MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* 6"-11.5" */
+#define USB2_PORT_MID { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* 3"-6" */
+#define USB2_PORT_SHORT { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_39MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_39MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX */
+#define USB2_PORT_TYPE_C { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Port with BC1.2 charge detect module / MUX */
+#define USB2_PORT_BC12_MUX { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Internal Flex Cable, 3"-5" + cable + 2" card */
+#define USB2_PORT_FLEX { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Docking, 3"-9" */
+#define USB2_PORT_DOCKING_LONG { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Docking, 3"-6" */
+#define USB2_PORT_DOCKING_SHORT { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_17MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_45MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
+#define USB2_PORT_DETACHABLE_TABLET { \
+ .enable = 1, \
+ .tx_bias = USB2_BIAS_17MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_45MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+struct usb3_port_config {
+ uint8_t enable;
+ uint8_t tx_de_emp;
+ uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+ .enable = 0, \
+ .tx_de_emp = 0x00, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT { \
+ .enable = 1, \
+ .tx_de_emp = 0x29, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#endif
More information about the coreboot-gerrit
mailing list