[coreboot-gerrit] New patch to review for coreboot: northbridge/intel/sandybridge: support both Sandy&Ivy on one board
Iru Cai (mytbk920423@gmail.com)
gerrit at coreboot.org
Sun Oct 18 18:02:35 CEST 2015
Iru Cai (mytbk920423 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12087
-gerrit
commit 88318c45171c2103a00982ecdfcc86345c225f9b
Author: Iru Cai <mytbk920423 at gmail.com>
Date: Sun Oct 18 23:40:34 2015 +0800
northbridge/intel/sandybridge: support both Sandy&Ivy on one board
Sandy and Ivy Bridge processors use the same socket,
and a mainboard with the socket can support both types
of CPUs. However, they use different native graphics init
code and cause a crashing if running the wrong code.
So it needs a detecting and selecting the right code to run.
This patch will add some more code in romstage.
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
---
src/northbridge/intel/sandybridge/Makefile.inc | 2 ++
src/northbridge/intel/sandybridge/gma.c | 10 ++++++++--
src/northbridge/intel/sandybridge/gma.h | 2 ++
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 4 ++--
4 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 52fe23c..a7322f6 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -23,6 +23,8 @@ ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
+ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c
+ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_ivybridge_lvds.c
ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c
ramstage-y += acpi.c
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index d1779db..b7a5ef4 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -595,8 +595,14 @@ static void gma_func0_init(struct device *dev)
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
- int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase,
- mmiobase, graphics_base);
+ int lightup_ok;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase,
+ mmiobase, graphics_base);
+ } else {
+ lightup_ok = i915lightup_ivy(&conf->gfx, physbase, iobase,
+ mmiobase, graphics_base);
+ }
if (lightup_ok)
gfx_set_init_done(1);
}
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index d8e19e4..91979a5 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -118,3 +118,5 @@ struct i915_gpu_controller_info;
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 physbase, u16 pio, u8 *mmio, u32 lfb);
+int i915lightup_ivy(const struct i915_gpu_controller_info *info,
+ u32 phybase, u16 pio, u8 *mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 101a3c1..7137c5b 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -157,8 +157,8 @@ static void enable_port(u8 *mmio)
read32(mmio + 0xc4000);
}
-int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
+int i915lightup_ivy(const struct i915_gpu_controller_info *info,
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
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