[coreboot-gerrit] New patch to review for coreboot: cpu/amd: Repace 0x259 by macro MTRR_FIX_16K_A0000
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Sun Oct 18 13:41:55 CEST 2015
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12086
-gerrit
commit dca80a81eb82b6de63a1f9822b0403b1096eb9fe
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Sun Oct 18 13:41:12 2015 +0200
cpu/amd: Repace 0x259 by macro MTRR_FIX_16K_A0000
Change-Id: I52098df804bae1b2b559404346b09b0156a5f27d
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/cpu/amd/agesa/family14/model_14_init.c | 2 +-
src/cpu/amd/agesa/family15/model_15_init.c | 4 ++--
src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +-
src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +-
src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +-
src/cpu/amd/agesa/s3_mtrr.c | 4 ++--
src/cpu/amd/pi/00630F01/model_15_init.c | 2 +-
src/cpu/amd/pi/00660F01/model_15_init.c | 2 +-
src/cpu/amd/pi/00730F01/model_16_init.c | 2 +-
src/cpu/amd/pi/s3_resume.c | 4 ++--
10 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index a087d2e..8dc3b5c 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -61,7 +61,7 @@ static void model_14_init(device_t dev)
/* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.hi = msr.lo = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index 53e0ab2..614f90e 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -50,13 +50,13 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
for (msrno = 0x268; msrno <= 0x26f; msrno++)
wrmsr (msrno, msr);
msr.lo = 0x04040404; msr.hi = 0x04040404;
- wrmsr(0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
/* disable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c
index 2190a3e..6d46fff 100644
--- a/src/cpu/amd/agesa/family15rl/model_15_init.c
+++ b/src/cpu/amd/agesa/family15rl/model_15_init.c
@@ -60,7 +60,7 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index f4b0a26..ebc321a 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -59,7 +59,7 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index ae2e0be..3b002c8 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -57,7 +57,7 @@ static void model_16_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/agesa/s3_mtrr.c b/src/cpu/amd/agesa/s3_mtrr.c
index af23125..329de59 100644
--- a/src/cpu/amd/agesa/s3_mtrr.c
+++ b/src/cpu/amd/agesa/s3_mtrr.c
@@ -48,7 +48,7 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
/* Fixed MTRRs */
write_mtrr(&nvram_pos, 0x250);
write_mtrr(&nvram_pos, 0x258);
- write_mtrr(&nvram_pos, 0x259);
+ write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
for (i = 0x268; i < 0x270; i++)
write_mtrr(&nvram_pos, i);
@@ -105,7 +105,7 @@ void restore_mtrr(void)
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
- wrmsr(0x259, msr_data);
+ wrmsr(MTRR_FIX_16K_A0000, msr_data);
for (msr = 0x268; msr <= 0x26F; msr++) {
msr_data.lo = *msrPtr;
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index e2ba65e..93db61d 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -57,7 +57,7 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 602b900..388e7c4 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -72,7 +72,7 @@ static void model_15_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 453d985..e66f8f0 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -58,7 +58,7 @@ static void model_16_init(device_t dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr (MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(0x250, msr);
wrmsr(0x258, msr);
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
index 88b5713..a6a0cd1 100644
--- a/src/cpu/amd/pi/s3_resume.c
+++ b/src/cpu/amd/pi/s3_resume.c
@@ -105,7 +105,7 @@ void restore_mtrr(void)
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
- wrmsr(0x259, msr_data);
+ wrmsr(MTRR_FIX_16K_A0000, msr_data);
for (msr = 0x268; msr <= 0x26F; msr++) {
msr_data.lo = *msrPtr;
@@ -199,7 +199,7 @@ void OemAgesaSaveMtrr(void)
/* Fixed MTRRs */
write_mtrr(&nvram_pos, 0x250);
write_mtrr(&nvram_pos, 0x258);
- write_mtrr(&nvram_pos, 0x259);
+ write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
for (i = 0x268; i < 0x270; i++)
write_mtrr(&nvram_pos, i);
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