[coreboot-gerrit] Patch merged into coreboot/master: armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 3414561f00f49266580fa9372a24ef8578c7d932
Author: Paul Kocialkowski <contact at paulk.fr>
Date:   Tue Sep 22 22:16:33 2015 +0200

    armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
    
    Some registers only allow word-sized or half-word-sized operations and will
    cause a data fault when accessed with byte-sized operations.
    However, the compiler may or may not break such an operation into smaller
    (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
    32 bit read/write and half-word-sized operations for 16 bit read/write.
    
    This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.
    
    The definitions for byte-sized memory operations are also adapted to stay
    consistent with the rest.
    
    Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
    Reviewed-on: http://review.coreboot.org/11698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/11698 for details.

-gerrit