[coreboot-gerrit] New patch to review for coreboot: intel/fsp_baytrail: Load microcode in bootblock

[York Yang (york.yang@intel.com)]

York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11896

-gerrit

commit 2a3d213d900302dcee73f23c0283feaa061c2592
Author: York Yang <york.yang at intel.com>
Date:   Wed Oct 14 07:00:30 2015 -0700

    intel/fsp_baytrail: Load microcode in bootblock
    
    Load microcode in coreboot bootblock before any caching so FSP TempRamInit
    API can return success only when a microcode has been loaded. It resolve
    the scenario that always assuming CAR is setup even the TempRamInit API
    returns failure.
    
    Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81
    Signed-off-by: York Yang <york.yang at intel.com>
---
 src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 50d321b..a43ca0d 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -22,6 +22,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/intel/microcode/microcode.c>
 #include <baytrail/iosf.h>
 #include <baytrail/pci_devs.h>
 #include <baytrail/spi.h>
@@ -119,6 +120,9 @@ static void bootblock_cpu_init(void)
 
 	check_for_warm_reset();
 
+	/* Load microcode before any caching. */
+	intel_update_microcode_from_cbfs();
+
 	/* Allow memory-mapped PCI config access. */
 	setup_mmconfig();
 	enable_rom_caching();