[coreboot-gerrit] Patch set updated for coreboot: mainboard: Add support for Advantech SOM-6896
George McCollister (george.mccollister@gmail.com)
gerrit at coreboot.org
Mon Oct 12 20:49:07 CET 2015
George McCollister (george.mccollister at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11802
-gerrit
commit adc784cb89db2e8da39e998f2bfe566925a4b55b
Author: George McCollister <george.mccollister at gmail.com>
Date: Mon Oct 5 16:05:57 2015 -0500
mainboard: Add support for Advantech SOM-6896
Coreboot files are based on wtm2.
This board is able to boot Linux with working SATA, USB and VGA. I
wasn't able to find a working VGA rom so VGA doesn't work until
booted into Linux. The onboard Ethernet does not currently work, however a
PCIe NIC can be used.
Tested with:
P/N: SOM-6896C7-U2A1E
BLOBs from factory BIOS (descriptor, me, gbe)
BLOBs from yuna (mrc.bin, refcode)
Payload: u-boot (patches coming soon)
Distro: Ubuntu 15.04 installed on a SATA SSD
Kernel: 3.19.0-15-generic
Not tested:
Power management
I2C
SPI
Audio In
HDMI/DP
Change-Id: I3c2cd05de3d9b7585d952464810c7e625641f6c6
Signed-off-by: George McCollister <george.mccollister at gmail.com>
---
src/mainboard/advantech/Kconfig | 16 ++
src/mainboard/advantech/Kconfig.name | 2 +
src/mainboard/advantech/som-6896/Kconfig | 33 +++
src/mainboard/advantech/som-6896/Kconfig.name | 2 +
src/mainboard/advantech/som-6896/Makefile.inc | 2 +
src/mainboard/advantech/som-6896/acpi/ec.asl | 5 +
.../advantech/som-6896/acpi/mainboard.asl | 23 ++
src/mainboard/advantech/som-6896/acpi/superio.asl | 1 +
src/mainboard/advantech/som-6896/acpi/thermal.asl | 242 +++++++++++++++++++++
src/mainboard/advantech/som-6896/acpi_tables.c | 57 +++++
src/mainboard/advantech/som-6896/board_info.txt | 5 +
src/mainboard/advantech/som-6896/cmos.layout | 76 +++++++
src/mainboard/advantech/som-6896/devicetree.cb | 66 ++++++
src/mainboard/advantech/som-6896/dsdt.asl | 54 +++++
src/mainboard/advantech/som-6896/fadt.c | 46 ++++
src/mainboard/advantech/som-6896/gpio.h | 120 ++++++++++
src/mainboard/advantech/som-6896/hda_verb.c | 67 ++++++
src/mainboard/advantech/som-6896/mainboard.c | 49 +++++
src/mainboard/advantech/som-6896/pei_data.c | 53 +++++
src/mainboard/advantech/som-6896/romstage.c | 41 ++++
src/mainboard/advantech/som-6896/thermal.h | 53 +++++
21 files changed, 1013 insertions(+)
diff --git a/src/mainboard/advantech/Kconfig b/src/mainboard/advantech/Kconfig
new file mode 100644
index 0000000..13051d8
--- /dev/null
+++ b/src/mainboard/advantech/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_ADVANTECH
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/advantech/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/advantech/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Advantech"
+
+endif # VENDOR_ADVANTECH
diff --git a/src/mainboard/advantech/Kconfig.name b/src/mainboard/advantech/Kconfig.name
new file mode 100644
index 0000000..8862ffc
--- /dev/null
+++ b/src/mainboard/advantech/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ADVANTECH
+ bool "Advantech"
diff --git a/src/mainboard/advantech/som-6896/Kconfig b/src/mainboard/advantech/som-6896/Kconfig
new file mode 100644
index 0000000..58c702f
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Kconfig
@@ -0,0 +1,33 @@
+if BOARD_ADVANTECH_SOM_6896
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_INTEL_BROADWELL
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select INTEL_INT15
+
+config MAINBOARD_DIR
+ string
+ default advantech/som-6896
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "SOM-6896"
+
+config MAX_CPUS
+ int
+ default 8
+
+config HAVE_IFD_BIN
+ bool
+ default y
+
+config HAVE_ME_BIN
+ bool
+ default y
+
+endif # BOARD_ADVANTECH_SOM_6896
diff --git a/src/mainboard/advantech/som-6896/Kconfig.name b/src/mainboard/advantech/som-6896/Kconfig.name
new file mode 100644
index 0000000..044b184
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ADVANTECH_SOM_6896
+ bool "SOM-6896"
diff --git a/src/mainboard/advantech/som-6896/Makefile.inc b/src/mainboard/advantech/som-6896/Makefile.inc
new file mode 100644
index 0000000..f631a3b
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
diff --git a/src/mainboard/advantech/som-6896/acpi/ec.asl b/src/mainboard/advantech/som-6896/acpi/ec.asl
new file mode 100644
index 0000000..acb9ad7
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/ec.asl
@@ -0,0 +1,5 @@
+/*
+ * The Advantech som-6896 uses the IT8528e.
+ * If/when enough information is available this file
+ * will be completed.
+ */
diff --git a/src/mainboard/advantech/som-6896/acpi/mainboard.asl b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
new file mode 100644
index 0000000..0140343
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake from deep sleep via GPIO27
+ Name(_PRW, Package(){27, 4})
+}
diff --git a/src/mainboard/advantech/som-6896/acpi/superio.asl b/src/mainboard/advantech/som-6896/acpi/superio.asl
new file mode 100644
index 0000000..99293eb
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/superio.asl
@@ -0,0 +1 @@
+/* There is no Super I/O configured at this time. */
diff --git a/src/mainboard/advantech/som-6896/acpi/thermal.asl b/src/mainboard/advantech/som-6896/acpi/thermal.asl
new file mode 100644
index 0000000..06a6f00
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/thermal.asl
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+#include "../thermal.h"
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 0 seconds
+ Name (_TZP, 0)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (CTOK (30))
+ }
+
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (FAN0_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN0_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (FAN1_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN1_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC2) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (CTOK (FAN2_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN2_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC3) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (CTOK (FAN3_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN3_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC4) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (CTOK (FAN4_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN4_THRESHOLD_ON))
+ }
+ }
+
+ Name (_AL0, Package () { FAN0 })
+ Name (_AL1, Package () { FAN1 })
+ Name (_AL2, Package () { FAN2 })
+ Name (_AL3, Package () { FAN3 })
+ Name (_AL4, Package () { FAN4 })
+
+ PowerResource (FNP0, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (0, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP1, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP2, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP3, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP4, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ Device (FAN0)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 0)
+ Name (_PR0, Package () { FNP0 })
+ }
+
+ Device (FAN1)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 1)
+ Name (_PR0, Package () { FNP1 })
+ }
+
+ Device (FAN2)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 2)
+ Name (_PR0, Package () { FNP2 })
+ }
+
+ Device (FAN3)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 3)
+ Name (_PR0, Package () { FNP3 })
+ }
+
+ Device (FAN4)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 4)
+ Name (_PR0, Package () { FNP4 })
+ }
+ }
+}
diff --git a/src/mainboard/advantech/som-6896/acpi_tables.c b/src/mainboard/advantech/som-6896/acpi_tables.c
new file mode 100644
index 0000000..c72fdb8
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi_tables.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include "thermal.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
diff --git a/src/mainboard/advantech/som-6896/board_info.txt b/src/mainboard/advantech/som-6896/board_info.txt
new file mode 100644
index 0000000..583c34c
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/board_info.txt
@@ -0,0 +1,5 @@
+Category: half
+Board name: SOM-6896
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: y
diff --git a/src/mainboard/advantech/som-6896/cmos.layout b/src/mainboard/advantech/som-6896/cmos.layout
new file mode 100644
index 0000000..57b6ac1
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/cmos.layout
@@ -0,0 +1,76 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/advantech/som-6896/devicetree.cb b/src/mainboard/advantech/som-6896/devicetree.cb
new file mode 100644
index 0000000..d87c225
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/devicetree.cb
@@ -0,0 +1,66 @@
+chip soc/intel/broadwell
+
+ # Disable digital port d
+ register "gpu_dp_d_hotplug" = "0x00"
+
+ # Disable digital port c
+ register "gpu_dp_c_hotplug" = "0x00"
+
+ # Disable digital port b
+ register "gpu_dp_b_hotplug" = "0x00"
+
+ register "pirqa_routing" = "0xa"
+ register "pirqb_routing" = "0xa"
+ register "pirqc_routing" = "0xa"
+ register "pirqd_routing" = "0xa"
+ register "pirqe_routing" = "0xa"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0xa"
+ register "pirqh_routing" = "0xa"
+
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpe0_en_1" = "0x00000400"
+ register "gpe0_en_2" = "0x00000000"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 off end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 on end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 on end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/advantech/som-6896/dsdt.asl b/src/mainboard/advantech/som-6896/dsdt.asl
new file mode 100644
index 0000000..9e87506
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/broadwell/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/broadwell/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // CPU
+ #include <soc/intel/broadwell/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/broadwell/acpi/systemagent.asl>
+ #include <soc/intel/broadwell/acpi/pch.asl>
+ }
+ }
+
+ // Thermal handler
+ #include "acpi/thermal.asl"
+
+ // Chipset specific sleep states
+ #include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/advantech/som-6896/fadt.c b/src/mainboard/advantech/som-6896/fadt.c
new file mode 100644
index 0000000..b2d2025
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/advantech/som-6896/gpio.h b/src/mainboard/advantech/som-6896/gpio.h
new file mode 100644
index 0000000..99d5acc
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ADVANTECH_SOM_6896_GPIO_H
+#define ADVANTECH_SOM_6896_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */
+ PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */
+ PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */
+ PCH_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */
+ PCH_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */
+ PCH_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */
+ PCH_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */
+ PCH_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */
+ PCH_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */
+ PCH_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */
+ PCH_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */
+ PCH_GPIO_UNUSED, /* 11: AMB_THRM_R_N */
+ PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */
+ PCH_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */
+ PCH_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */
+ PCH_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */
+ PCH_GPIO_OUT_HIGH, /* 16: LAN_RST_N */
+ PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */
+ PCH_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */
+ PCH_GPIO_INPUT, /* 19: EC_IN_RW */
+ PCH_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */
+ PCH_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */
+ PCH_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */
+ PCH_GPIO_NATIVE, /* 23: CK_REQ_P5_N */
+ PCH_GPIO_OUT_LOW, /* 24: ME_PG_LED */
+ PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_N */
+ PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */
+ PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */
+ PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */
+ PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */
+ PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */
+ PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */
+ PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */
+ PCH_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */
+ PCH_GPIO_INPUT, /* 34: ESATA_DET_N */
+ PCH_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */
+ PCH_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */
+ PCH_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */
+ PCH_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */
+ PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */
+ PCH_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */
+ PCH_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */
+ PCH_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */
+ PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */
+ PCH_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */
+ PCH_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */
+ PCH_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */
+ PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */
+ PCH_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */
+ PCH_GPIO_INPUT, /* 49: COMBO_JD */
+ PCH_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */
+ PCH_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */
+ PCH_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */
+ PCH_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */
+ PCH_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */
+ PCH_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */
+ PCH_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */
+ PCH_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */
+ PCH_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */
+ PCH_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */
+ PCH_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */
+ PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */
+ PCH_GPIO_NATIVE, /* 62: SUS_CK */
+ PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */
+ PCH_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */
+ PCH_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */
+ PCH_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */
+ PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */
+ PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */
+ PCH_GPIO_NATIVE, /* 74: SML1_DATA */
+ PCH_GPIO_NATIVE, /* 75: SML1_CK */
+ PCH_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */
+ PCH_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */
+ PCH_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */
+ PCH_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */
+ PCH_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */
+ PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */
+ PCH_GPIO_NATIVE, /* 82: H_RCIN_N */
+ PCH_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */
+ PCH_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */
+ PCH_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */
+ PCH_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */
+ PCH_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */
+ PCH_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */
+ PCH_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */
+ PCH_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */
+ PCH_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */
+ PCH_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */
+ PCH_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */
+ PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/advantech/som-6896/hda_verb.c b/src/mainboard/advantech/som-6896/hda_verb.c
new file mode 100644
index 0000000..6a7ae31
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/hda_verb.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10134210, /* Codec Vendor / Device ID: Cirrus Logic CS4210 */
+ 0x10134210, /* Subsystem ID */
+ 0x00000007, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
+ AZALIA_SUBVENDOR(0x0, 0x10134210),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */
+ AZALIA_PIN_CFG(0x0, 0x05, 0x022120f0),
+
+ /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */
+ AZALIA_PIN_CFG(0x0, 0x06, 0x90170010),
+
+ /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */
+ AZALIA_PIN_CFG(0x0, 0x07, 0x02a120f0),
+
+ /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */
+ AZALIA_PIN_CFG(0x0, 0x08, 0x77a70037),
+
+ /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x77a6003e),
+
+ /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x434510f0),
+
+ /* coreboot specific header */
+ 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x0, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/advantech/som-6896/mainboard.c b/src/mainboard/advantech/som-6896/mainboard.c
new file mode 100644
index 0000000..67a7bc6
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/mainboard.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+/* mainboard_enable is executed as first thing after enumerate_buses(). */
+
+static void mainboard_enable(device_t dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
+ GMA_INT15_PANEL_FIT_CENTERING,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT,
+ 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/advantech/som-6896/pei_data.c b/src/mainboard/advantech/som-6896/pei_data.c
new file mode 100644
index 0000000..7408d4b
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/pei_data.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 3;
+
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[2] = 0xa0;
+
+ pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+
+ pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/advantech/som-6896/romstage.c b/src/mainboard/advantech/som-6896/romstage.c
new file mode 100644
index 0000000..3c9bb36
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/romstage.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include "gpio.h"
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ struct pei_data pei_data;
+
+ post_code(0x32);
+
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
+
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ rp->pei_data = &pei_data;
+
+ romstage_common(rp);
+}
diff --git a/src/mainboard/advantech/som-6896/thermal.h b/src/mainboard/advantech/som-6896/thermal.h
new file mode 100644
index 0000000..cda50df
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/thermal.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ADVANTECH_SOM_6896_THERMAL_H
+#define ADVANTECH_SOM_6896_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF 0
+#define FAN4_THRESHOLD_ON 0
+#define FAN4_PWM 0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF 48
+#define FAN3_THRESHOLD_ON 55
+#define FAN3_PWM 0x40
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF 52
+#define FAN2_THRESHOLD_ON 64
+#define FAN2_PWM 0x80
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF 60
+#define FAN1_THRESHOLD_ON 68
+#define FAN1_PWM 0xb0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF 66
+#define FAN0_THRESHOLD_ON 78
+#define FAN0_PWM 0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 100
+
+#endif
More information about the coreboot-gerrit
mailing list