[coreboot-gerrit] New patch to review for coreboot: mainboard: Copying wtm2 to som-6896
George McCollister (george.mccollister@gmail.com)
gerrit at coreboot.org
Mon Oct 5 21:31:06 CET 2015
George McCollister (george.mccollister at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11804
-gerrit
commit 61ef0ad8c720cc40bfafc10359aaec80b488a1c1
Author: George McCollister <george.mccollister at gmail.com>
Date: Mon Oct 5 16:05:57 2015 -0500
mainboard: Copying wtm2 to som-6896
Per Paul Menzel's request I'm copying intel/wtm2 to advantech/som-6896
to make it easier to review my som-6896 additions which are based on
wtm2.
I disabled checkpatch.pl for this commit since as is, wtm2 throws a
bunch of errors.
Change-Id: Ia2172830f493465c2d92ea594cf1e9fa52f5d94c
Signed-off-by: George McCollister <george.mccollister at gmail.com>
---
src/mainboard/advantech/som-6896/Kconfig | 45 ++++
src/mainboard/advantech/som-6896/Kconfig.name | 2 +
src/mainboard/advantech/som-6896/Makefile.inc | 27 +++
src/mainboard/advantech/som-6896/acpi/chromeos.asl | 24 ++
src/mainboard/advantech/som-6896/acpi/ec.asl | 37 ++++
.../advantech/som-6896/acpi/mainboard.asl | 27 +++
src/mainboard/advantech/som-6896/acpi/platform.asl | 72 ++++++
src/mainboard/advantech/som-6896/acpi/superio.asl | 20 ++
src/mainboard/advantech/som-6896/acpi/thermal.asl | 246 +++++++++++++++++++++
src/mainboard/advantech/som-6896/acpi_tables.c | 61 +++++
src/mainboard/advantech/som-6896/board_info.txt | 2 +
src/mainboard/advantech/som-6896/chromeos.c | 66 ++++++
src/mainboard/advantech/som-6896/cmos.layout | 115 ++++++++++
src/mainboard/advantech/som-6896/devicetree.cb | 66 ++++++
src/mainboard/advantech/som-6896/dsdt.asl | 64 ++++++
src/mainboard/advantech/som-6896/fadt.c | 50 +++++
src/mainboard/advantech/som-6896/gpio.h | 124 +++++++++++
src/mainboard/advantech/som-6896/graphics.c | 87 ++++++++
src/mainboard/advantech/som-6896/hda_verb.c | 71 ++++++
src/mainboard/advantech/som-6896/i915.c | 232 +++++++++++++++++++
src/mainboard/advantech/som-6896/intel_dp.c | 167 ++++++++++++++
src/mainboard/advantech/som-6896/mainboard.c | 51 +++++
src/mainboard/advantech/som-6896/pei_data.c | 57 +++++
src/mainboard/advantech/som-6896/romstage.c | 45 ++++
src/mainboard/advantech/som-6896/thermal.h | 57 +++++
25 files changed, 1815 insertions(+)
diff --git a/src/mainboard/advantech/som-6896/Kconfig b/src/mainboard/advantech/som-6896/Kconfig
new file mode 100644
index 0000000..e739efa
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_INTEL_WTM2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_INTEL_BROADWELL
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_INT15
+
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+ select CHROMEOS_VBNV_CMOS
+
+config MAINBOARD_DIR
+ string
+ default intel/wtm2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "WHITETIP MOUNTAIN 2"
+
+
+config MAX_CPUS
+ int
+ default 16
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+endif # BOARD_INTEL_WTM2
diff --git a/src/mainboard/advantech/som-6896/Kconfig.name b/src/mainboard/advantech/som-6896/Kconfig.name
new file mode 100644
index 0000000..d0a474d
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_WTM2
+ bool "Whitetip Mountain 2 CRB"
diff --git a/src/mainboard/advantech/som-6896/Makefile.inc b/src/mainboard/advantech/som-6896/Makefile.inc
new file mode 100644
index 0000000..78bd51a
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-y += chromeos.c
+ramstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
+
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
diff --git a/src/mainboard/advantech/som-6896/acpi/chromeos.asl b/src/mainboard/advantech/som-6896/acpi/chromeos.asl
new file mode 100644
index 0000000..9b7727e
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/chromeos.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Name(OIPG, Package() {
+ Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
+ Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
+ Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
+})
diff --git a/src/mainboard/advantech/som-6896/acpi/ec.asl b/src/mainboard/advantech/som-6896/acpi/ec.asl
new file mode 100644
index 0000000..9ae5951
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/ec.asl
@@ -0,0 +1,37 @@
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x03),
+ ACPR, 1, // AC Power (1=present)
+ , 2,
+ CFAN, 1, // CPU Fan (1=on)
+ , 2,
+ LIDS, 1, // Lid State (1=open)
+ , 1,
+ SPTR, 8, // SMBUS Protocol Register
+ SSTS, 8, // SMBUS Status Register
+ SADR, 8, // SMBUS Address Register
+ SCMD, 8, // SMBUS Command Register
+ SBFR, 256, // SMBUS Block Buffer
+ SCNT, 8, // SMBUS Block Count
+
+ Offset (0x3a),
+ ECMD, 8, // EC Command Register
+
+ Offset (0x82),
+ PECL, 8, // PECI fractional (1/64 Celsius)
+ PECH, 8, // PECI integer (Celsius)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+}
diff --git a/src/mainboard/advantech/som-6896/acpi/mainboard.asl b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
new file mode 100644
index 0000000..f37b8b7
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake from deep sleep via GPIO27
+ Name(_PRW, Package(){27, 4})
+}
diff --git a/src/mainboard/advantech/som-6896/acpi/platform.asl b/src/mainboard/advantech/som-6896/acpi/platform.asl
new file mode 100644
index 0000000..24ddc91
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/platform.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/advantech/som-6896/acpi/superio.asl b/src/mainboard/advantech/som-6896/acpi/superio.asl
new file mode 100644
index 0000000..c9c14e4
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/superio.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Values should match those defined in devicetree.cb */
diff --git a/src/mainboard/advantech/som-6896/acpi/thermal.asl b/src/mainboard/advantech/som-6896/acpi/thermal.asl
new file mode 100644
index 0000000..061347c
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi/thermal.asl
@@ -0,0 +1,246 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+// Thermal Zone
+#include "../thermal.h"
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 0 seconds
+ Name (_TZP, 0)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (CTOK (30))
+ }
+
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (FAN0_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN0_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (FAN1_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN1_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC2) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (CTOK (FAN2_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN2_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC3) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (CTOK (FAN3_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN3_THRESHOLD_ON))
+ }
+ }
+
+ Method (_AC4) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (CTOK (FAN4_THRESHOLD_OFF))
+ } Else {
+ Return (CTOK (FAN4_THRESHOLD_ON))
+ }
+ }
+
+ Name (_AL0, Package () { FAN0 })
+ Name (_AL1, Package () { FAN1 })
+ Name (_AL2, Package () { FAN2 })
+ Name (_AL3, Package () { FAN3 })
+ Name (_AL4, Package () { FAN4 })
+
+ PowerResource (FNP0, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (0, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP1, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (1, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP2, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 2)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (2, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP3, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 3)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (3, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ PowerResource (FNP4, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 4)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ Method (_OFF) {
+ Store (4, \FLVL)
+ Notify (\_TZ.THRM, 0x81)
+ }
+ }
+
+ Device (FAN0)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 0)
+ Name (_PR0, Package () { FNP0 })
+ }
+
+ Device (FAN1)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 1)
+ Name (_PR0, Package () { FNP1 })
+ }
+
+ Device (FAN2)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 2)
+ Name (_PR0, Package () { FNP2 })
+ }
+
+ Device (FAN3)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 3)
+ Name (_PR0, Package () { FNP3 })
+ }
+
+ Device (FAN4)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 4)
+ Name (_PR0, Package () { FNP4 })
+ }
+ }
+}
diff --git a/src/mainboard/advantech/som-6896/acpi_tables.c b/src/mainboard/advantech/som-6896/acpi_tables.c
new file mode 100644
index 0000000..a960397
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/acpi_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include "thermal.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ return acpi_madt_irq_overrides(current);
+}
diff --git a/src/mainboard/advantech/som-6896/board_info.txt b/src/mainboard/advantech/som-6896/board_info.txt
new file mode 100644
index 0000000..64e00fa
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/board_info.txt
@@ -0,0 +1,2 @@
+Category: eval
+Release year: 2013
diff --git a/src/mainboard/advantech/som-6896/chromeos.c b/src/mainboard/advantech/som-6896/chromeos.c
new file mode 100644
index 0000000..fe80063
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/chromeos.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <string.h>
+#include <bootmode.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+
+/* Compile-time settings for developer and recovery mode. */
+#define DEV_MODE_SETTING 1
+#define REC_MODE_SETTING 0
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio *gpio;
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ gpio = gpios->gpios;
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", REC_MODE_SETTING);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", DEV_MODE_SETTING);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+ return DEV_MODE_SETTING;
+}
+
+int get_recovery_mode_switch(void)
+{
+ return REC_MODE_SETTING;
+}
+
+int get_write_protect_state(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/advantech/som-6896/cmos.layout b/src/mainboard/advantech/som-6896/cmos.layout
new file mode 100644
index 0000000..23faeeb
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/cmos.layout
@@ -0,0 +1,115 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/advantech/som-6896/devicetree.cb b/src/mainboard/advantech/som-6896/devicetree.cb
new file mode 100644
index 0000000..54b2bff
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/devicetree.cb
@@ -0,0 +1,66 @@
+chip soc/intel/broadwell
+
+ # Enable DisplayPort 1 Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable DisplayPort 0 Hotplug with 6ms pulse
+ register "gpu_dp_c_hotplug" = "0x06"
+
+ # Enable DVI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpe0_en_1" = "0x00000400"
+ register "gpe0_en_2" = "0x00000000"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
+
+ register "sata_port_map" = "0x2"
+ register "sio_acpi_mode" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 off end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1d.0 off end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 on end # SMBus
+ device pci 1f.6 on end # Thermal
+ end
+end
diff --git a/src/mainboard/advantech/som-6896/dsdt.asl b/src/mainboard/advantech/som-6896/dsdt.asl
new file mode 100644
index 0000000..ac12eb7
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/dsdt.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <soc/intel/broadwell/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // CPU
+ #include <soc/intel/broadwell/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/broadwell/acpi/systemagent.asl>
+ #include <soc/intel/broadwell/acpi/pch.asl>
+ }
+ }
+
+ // Thermal handler
+ #include "acpi/thermal.asl"
+
+ // Chrome OS specific
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chipset specific sleep states
+ #include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/advantech/som-6896/fadt.c b/src/mainboard/advantech/som-6896/fadt.c
new file mode 100644
index 0000000..61e0439
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/fadt.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/advantech/som-6896/gpio.h b/src/mainboard/advantech/som-6896/gpio.h
new file mode 100644
index 0000000..8abb593
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/gpio.h
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef INTEL_WTM2_GPIO_H
+#define INTEL_WTM2_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */
+ PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */
+ PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */
+ PCH_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */
+ PCH_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */
+ PCH_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */
+ PCH_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */
+ PCH_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */
+ PCH_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */
+ PCH_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */
+ PCH_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */
+ PCH_GPIO_UNUSED, /* 11: AMB_THRM_R_N */
+ PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */
+ PCH_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */
+ PCH_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */
+ PCH_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */
+ PCH_GPIO_OUT_HIGH, /* 16: LAN_RST_N */
+ PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */
+ PCH_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */
+ PCH_GPIO_INPUT, /* 19: EC_IN_RW */
+ PCH_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */
+ PCH_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */
+ PCH_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */
+ PCH_GPIO_NATIVE, /* 23: CK_REQ_P5_N */
+ PCH_GPIO_OUT_LOW, /* 24: ME_PG_LED */
+ PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_N */
+ PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */
+ PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */
+ PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */
+ PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */
+ PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */
+ PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */
+ PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */
+ PCH_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */
+ PCH_GPIO_INPUT, /* 34: ESATA_DET_N */
+ PCH_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */
+ PCH_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */
+ PCH_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */
+ PCH_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */
+ PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */
+ PCH_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */
+ PCH_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */
+ PCH_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */
+ PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */
+ PCH_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */
+ PCH_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */
+ PCH_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */
+ PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */
+ PCH_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */
+ PCH_GPIO_INPUT, /* 49: COMBO_JD */
+ PCH_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */
+ PCH_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */
+ PCH_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */
+ PCH_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */
+ PCH_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */
+ PCH_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */
+ PCH_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */
+ PCH_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */
+ PCH_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */
+ PCH_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */
+ PCH_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */
+ PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */
+ PCH_GPIO_NATIVE, /* 62: SUS_CK */
+ PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */
+ PCH_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */
+ PCH_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */
+ PCH_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */
+ PCH_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */
+ PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */
+ PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */
+ PCH_GPIO_NATIVE, /* 74: SML1_DATA */
+ PCH_GPIO_NATIVE, /* 75: SML1_CK */
+ PCH_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */
+ PCH_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */
+ PCH_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */
+ PCH_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */
+ PCH_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */
+ PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */
+ PCH_GPIO_NATIVE, /* 82: H_RCIN_N */
+ PCH_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */
+ PCH_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */
+ PCH_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */
+ PCH_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */
+ PCH_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */
+ PCH_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */
+ PCH_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */
+ PCH_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */
+ PCH_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */
+ PCH_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */
+ PCH_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */
+ PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */
+ PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/advantech/som-6896/graphics.c b/src/mainboard/advantech/som-6896/graphics.c
new file mode 100644
index 0000000..64baf18
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/graphics.c
@@ -0,0 +1,87 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc.
+*/
+/* this file was for the most part machine generated, and in future
+ * will be all machine generated. Avoid editing.
+ */
+#include <console/console.h>
+#include <drivers/intel/gma/i915.h>
+
+void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
+{
+
+ io_i915_write32(0x80000000,0x45400);
+ io_i915_write32(0x00000000,_CURACNTR);
+ io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
+ io_i915_write32(0x00000000,_DSPBCNTR);
+ io_i915_write32(0x80000000,CPU_VGACNTRL);
+ io_i915_write32(0x00000000,_DSPASIZE+0xc);
+ io_i915_write32(0x00000000,_DSPBSURF);
+ io_i915_write32(0x00000000,0x4f050);
+ io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
+ DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
+ DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
+ DP_SYNC_VS_HIGH |0x00000091,DP_A);
+ io_i915_write32(0x00200090,_FDI_RXA_MISC);
+ io_i915_write32(0x0a000000,_FDI_RXA_MISC);
+ /* not yet documented anywhere that we can find. */
+ io_i915_write32(0x00000070,0x46408);
+ io_i915_write32(0x04000000,0x42090);
+ io_i915_write32(0x40000000,0x4f050);
+ io_i915_write32(0x00000000,0x9840);
+ io_i915_write32(0xa4000000,0x42090);
+ io_i915_write32(0x00004000,0x42080);
+ io_i915_write32(0x00ffffff,0x64f80);
+ io_i915_write32(0x0007000e,0x64f84);
+ io_i915_write32(0x00d75fff,0x64f88);
+ io_i915_write32(0x000f000a,0x64f8c);
+ io_i915_write32(0x00c30fff,0x64f90);
+ io_i915_write32(0x00060006,0x64f94);
+ io_i915_write32(0x00aaafff,0x64f98);
+ io_i915_write32(0x001e0000,0x64f9c);
+ io_i915_write32(0x00ffffff,0x64fa0);
+ io_i915_write32(0x000f000a,0x64fa4);
+ io_i915_write32(0x00d75fff,0x64fa8);
+ io_i915_write32(0x00160004,0x64fac);
+ io_i915_write32(0x00c30fff,0x64fb0);
+ io_i915_write32(0x001e0000,0x64fb4);
+ io_i915_write32(0x00ffffff,0x64fb8);
+ io_i915_write32(0x00060006,0x64fbc);
+ io_i915_write32(0x00d75fff,0x64fc0);
+ io_i915_write32(0x001e0000,0x64fc4);
+ io_i915_write32(0x00ffffff,0x64e00);
+ io_i915_write32(0x0006000e,0x64e04);
+ io_i915_write32(0x00d75fff,0x64e08);
+ io_i915_write32(0x0005000a,0x64e0c);
+ io_i915_write32(0x00c30fff,0x64e10);
+ io_i915_write32(0x00040006,0x64e14);
+ io_i915_write32(0x80aaafff,0x64e18);
+ io_i915_write32(0x000b0000,0x64e1c);
+ io_i915_write32(0x00ffffff,0x64e20);
+ io_i915_write32(0x0005000a,0x64e24);
+ io_i915_write32(0x00d75fff,0x64e28);
+ io_i915_write32(0x000c0004,0x64e2c);
+ io_i915_write32(0x80c30fff,0x64e30);
+ io_i915_write32(0x000b0000,0x64e34);
+ io_i915_write32(0x00ffffff,0x64e38);
+ io_i915_write32(0x00040006,0x64e3c);
+ io_i915_write32(0x80d75fff,0x64e40);
+ io_i915_write32(0x000b0000,0x64e44);
+ /* end not yet documented. */
+ io_i915_write32(0x10000000,SDEISR+0x30);
+}
diff --git a/src/mainboard/advantech/som-6896/hda_verb.c b/src/mainboard/advantech/som-6896/hda_verb.c
new file mode 100644
index 0000000..1eb70c5
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/hda_verb.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210
+ 0x10134210, // Subsystem ID
+ 0x00000007, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
+ AZALIA_SUBVENDOR(0x0, 0x10134210),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */
+ AZALIA_PIN_CFG(0x0, 0x05, 0x022120f0),
+
+ /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */
+ AZALIA_PIN_CFG(0x0, 0x06, 0x90170010),
+
+ /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */
+ AZALIA_PIN_CFG(0x0, 0x07, 0x02a120f0),
+
+ /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */
+ AZALIA_PIN_CFG(0x0, 0x08, 0x77a70037),
+
+ /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x77a6003e),
+
+ /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x434510f0),
+
+ /* coreboot specific header */
+ 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x0, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/advantech/som-6896/i915.c b/src/mainboard/advantech/som-6896/i915.c
new file mode 100644
index 0000000..4a8d25b
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/i915.c
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <edid.h>
+#include <drivers/intel/gma/i915.h>
+
+/* how many bytes do we need for the framebuffer?
+ * Well, this gets messy. To get an exact answer, we have
+ * to ask the panel, but we'd rather zero the memory
+ * and set up the gtt while the panel powers up. So,
+ * we take a reasonable guess, secure in the knowledge that the
+ * MRC has to overestimate the number of bytes used.
+ * 8 MiB is a very safe guess. There may be a better way later, but
+ * fact is, the initial framebuffer is only very temporary. And taking
+ * a little long is ok; this is done much faster than the AUX
+ * channel is ready for IO.
+ */
+#define FRAME_BUFFER_BYTES (8*MiB)
+/* how many 4096-byte pages do we need for the framebuffer?
+ * There are hard ways to get this, and easy ways:
+ * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
+ * on this chip (and in fact every Intel graphics chip we've seen).
+ */
+#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
+
+static int verbose = 0;
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned short addrport;
+static unsigned short dataport;
+static unsigned int physbase;
+
+const u32 link_edid_data[] = {
+ 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
+ 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
+ 0x00545017, 0x01010000, 0x01010101, 0x01010101,
+ 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
+ 0xb510003a, 0x19000010, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
+ 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
+ 0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
+};
+
+static int ioread = 0, iowrite = 0;
+
+static char *regname(unsigned long addr)
+{
+ static char name[16];
+ snprintf(name, sizeof (name), "0x%lx", addr);
+ return name;
+}
+
+unsigned long io_i915_read32(unsigned long addr)
+{
+ unsigned long val;
+ outl(addr, addrport);
+ val = inl(dataport);
+ ioread += 2;
+ if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
+ return val;
+}
+
+void io_i915_write32(unsigned long val, unsigned long addr)
+{
+ if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
+ outl(addr, addrport);
+ outl(val, dataport);
+ iowrite += 2;
+}
+
+/* GTT is the Global Translation Table for the graphics pipeline.
+ * It is used to translate graphics addresses to physical
+ * memory addresses. As in the CPU, GTTs map 4K pages.
+ * The setgtt function adds a further bit of flexibility:
+ * it allows you to set a range (the first two parameters) to point
+ * to a physical address (third parameter);the physical address is
+ * incremented by a count (fourth parameter) for each GTT in the
+ * range.
+ * Why do it this way? For ultrafast startup,
+ * we can point all the GTT entries to point to one page,
+ * and set that page to 0s:
+ * memset(physbase, 0, 4096);
+ * setgtt(0, 4250, physbase, 0);
+ * this takes about 2 ms, and is a win because zeroing
+ * the page takes a up to 200 ms.
+ * This call sets the GTT to point to a linear range of pages
+ * starting at physbase.
+ */
+
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+ int i;
+
+ for(i = start; i < end; i++){
+ u32 word = base + i*inc;
+ io_i915_write32(word|1,(i*4)|1);
+ }
+}
+
+static unsigned long tickspermicrosecond = 1795;
+static unsigned long long globalstart;
+
+static unsigned long
+microseconds(unsigned long long start, unsigned long long end)
+{
+ unsigned long ret;
+ ret = ((end - start)/tickspermicrosecond);
+ return ret;
+}
+
+static unsigned long globalmicroseconds(void)
+{
+ return microseconds(globalstart, rdtscll());
+}
+
+static int i915_init_done = 0;
+
+int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
+ unsigned int gfx);
+
+int i915lightup(unsigned int pphysbase, unsigned int piobase,
+ unsigned int pmmio, unsigned int pgfx)
+{
+ int must_cycle_power = 0;
+
+ /* frame buffer pointer */
+ u32 *l;
+ int i;
+ unsigned long before_gtt, after_gtt;
+
+ mmio = (void *)pmmio;
+ addrport = piobase;
+ dataport = addrport + 4;
+ physbase = pphysbase;
+ graphics = pgfx;
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p"
+ "addrport %04x physbase %08x\n",
+ (void *)graphics, mmio, addrport, physbase);
+ globalstart = rdtscll();
+
+ /* turn it on. The VBIOS does it this way, so we hope that's ok. */
+ verbose = 0;
+ io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
+
+ /* the AUX channel needs a small amount of time to spin up.
+ * Rather than udelay, do some useful work:
+ * Zero out the frame buffer memory,
+ * and set the global translation table (GTT)
+ */
+ printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
+ FRAME_BUFFER_BYTES/sizeof(u32));
+ for(l = (u32 *)graphics, i = 0;
+ i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
+ l[i] = 0x1122ff;
+ }
+ printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
+ FRAME_BUFFER_PAGES, (void *)physbase);
+ before_gtt = globalmicroseconds();
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+ after_gtt = globalmicroseconds();
+
+ /* The reset is basically harmless, and can be
+ * repeated by the VBIOS in any event.
+ */
+
+ graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
+
+ /* failures after this point can return without
+ * powering off the panel.
+ */
+
+ if (1)
+ goto fail;
+ /* failures after this point MUST power off the panel
+ * and wait 600 ms.
+ */
+
+ i915_init_done = 1;
+ return i915_init_done;
+
+fail:
+ printk(BIOS_SPEW, "Graphics could not be started;");
+ if (must_cycle_power){
+ printk(BIOS_SPEW, "Turn off power and wait ...");
+ io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
+ udelay(600000);
+ }
+ printk(BIOS_SPEW, "Returning.\n");
+ return 0;
+
+}
diff --git a/src/mainboard/advantech/som-6896/intel_dp.c b/src/mainboard/advantech/som-6896/intel_dp.c
new file mode 100644
index 0000000..b389946
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/intel_dp.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2013 Google Inc.
+ * Copyright © 2008 Intel Corporation
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Keith Packard <keithp at keithp.com>
+ *
+ */
+
+#include <console/console.h>
+#include <stdint.h>
+#include <delay.h>
+#include <drivers/intel/gma/i915.h>
+
+u32
+pack_aux(u32 *src32, int src_bytes)
+{
+ u8 *src = (u8 *)src32;
+ int i;
+ u32 v = 0;
+
+ if (src_bytes > 4)
+ src_bytes = 4;
+ for (i = 0; i < src_bytes; i++)
+ v |= ((u32) src[i]) << ((3-i) * 8);
+ return v;
+}
+
+void
+unpack_aux(u32 src, u8 *dst, int dst_bytes)
+{
+
+ int i;
+ if (dst_bytes > 4)
+ dst_bytes = 4;
+ for (i = 0; i < dst_bytes; i++)
+ dst[i] = src >> ((3-i) * 8);
+}
+
+int
+intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
+ u8 *recv, int recv_size)
+{
+ int i;
+ int recv_bytes;
+ u32 status;
+ u32 aux_clock_divider;
+ int try, precharge = 5;
+
+ /* The clock divider is based off the hrawclk,
+ * and would like to run at 2MHz. So, take the
+ * hrawclk value and divide by 2 and use that
+ *
+ * Note that PCH attached eDP panels should use a 125MHz input
+ * clock divider.
+ */
+ /* 200 on link */
+ aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
+
+ /* Try to wait for any previous AUX channel activity */
+ for (try = 0; try < 3; try++) {
+ status = io_i915_read32(ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ udelay(1000);
+ }
+
+ if (try == 3) {
+ printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+ status = io_i915_read32(ch_ctl);
+ printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08x\n",
+ status);
+ return -1;
+ }
+
+ /* Must try at least 3 times according to DP spec */
+ for (try = 0; try < 5; try++) {
+ /* Load the send data into the aux channel data registers */
+ for (i = 0; i < send_bytes; i += 4)
+ io_i915_write32(send[i], ch_data + i);
+
+ /* Send the command and wait for it to complete */
+ io_i915_write32(
+ DP_AUX_CH_CTL_SEND_BUSY |
+ DP_AUX_CH_CTL_TIME_OUT_400us |
+ (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+ (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
+ for (;;) {
+ status = io_i915_read32(ch_ctl);
+ if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+ break;
+ udelay(100);
+ }
+
+ /* Clear done status and any errors */
+ io_i915_write32(
+ status |
+ DP_AUX_CH_CTL_DONE |
+ DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
+
+ if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
+ DP_AUX_CH_CTL_RECEIVE_ERROR))
+ continue;
+ if (status & DP_AUX_CH_CTL_DONE)
+ break;
+ }
+
+ if ((status & DP_AUX_CH_CTL_DONE) == 0) {
+ printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+ printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
+ return -1;
+ }
+
+ /* Check for timeout or receive error.
+ * Timeouts occur when the sink is not connected
+ */
+ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+ printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
+ return -1;
+ }
+
+ /* Timeouts occur when the device isn't connected, so they're
+ * "normal" -- don't fill the kernel log with these */
+ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
+ printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
+ printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
+ return -1;
+ }
+
+ /* Unload any bytes sent back from the other side */
+ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
+ DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
+ if (recv_bytes > recv_size)
+ recv_bytes = recv_size;
+
+ for (i = 0; i < recv_bytes; i += 4)
+ unpack_aux(io_i915_read32(ch_data + i),
+ recv + i, recv_bytes - i);
+
+ return recv_bytes;
+}
diff --git a/src/mainboard/advantech/som-6896/mainboard.c b/src/mainboard/advantech/som-6896/mainboard.c
new file mode 100644
index 0000000..6027ca7
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/mainboard.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/advantech/som-6896/pei_data.c b/src/mainboard/advantech/som-6896/pei_data.c
new file mode 100644
index 0000000..f35ca0e
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/pei_data.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ pei_data->spd_addresses[0] = 0xa2;
+ pei_data->spd_addresses[2] = 0xa2;
+
+ pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+ pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP,
+ USB_PORT_FRONT_PANEL);
+
+ pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/advantech/som-6896/romstage.c b/src/mainboard/advantech/som-6896/romstage.c
new file mode 100644
index 0000000..4435d64
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/romstage.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include "gpio.h"
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ struct pei_data pei_data;
+
+ post_code(0x32);
+
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
+
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ rp->pei_data = &pei_data;
+
+ romstage_common(rp);
+}
diff --git a/src/mainboard/advantech/som-6896/thermal.h b/src/mainboard/advantech/som-6896/thermal.h
new file mode 100644
index 0000000..5863466
--- /dev/null
+++ b/src/mainboard/advantech/som-6896/thermal.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef WTM2_THERMAL_H
+#define WTM2_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF 0
+#define FAN4_THRESHOLD_ON 0
+#define FAN4_PWM 0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF 48
+#define FAN3_THRESHOLD_ON 55
+#define FAN3_PWM 0x40
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF 52
+#define FAN2_THRESHOLD_ON 64
+#define FAN2_PWM 0x80
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF 60
+#define FAN1_THRESHOLD_ON 68
+#define FAN1_PWM 0xb0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF 66
+#define FAN0_THRESHOLD_ON 78
+#define FAN0_PWM 0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 100
+
+#endif
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