[coreboot-gerrit] New patch to review for coreboot: google/chell: Fix USB port assignment

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12324

-gerrit

commit e9858fa5c916db0fecb6fe983938db416aa586d2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Oct 30 17:55:05 2015 -0700

    google/chell: Fix USB port assignment
    
    The PCH pin names in the schematic were incorrectly labeled.
    
    BUG=chrome-os-partner:46289
    BRANCH=none
    TEST=build and boot on chell
    
    Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a
    Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/310061
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/chell/devicetree.cb | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index dfa588a..05e37bf 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -54,11 +54,11 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[4]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_MID"     # Type-A Port
-	register "usb2_ports[2]" = "USB2_PORT_FLEX"    # Camera
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
 	register "usb2_ports[3]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # SD
-	register "usb2_ports[5]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
+	register "usb2_ports[5]" = "USB2_PORT_MID"     # Type-A Port
+	register "usb2_ports[7]" = "USB2_PORT_FLEX"    # Camera
+	register "usb2_ports[9]" = "USB2_PORT_MID"     # SD
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2