[coreboot-gerrit] New patch to review for coreboot: 989822c intel/fsp_baytrail: Clarify naming of eMMC controllers
David Imhoff (dimhoff_devel@xs4all.nl)
gerrit at coreboot.org
Sun May 10 17:13:49 CEST 2015
David Imhoff (dimhoff_devel at xs4all.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10166
-gerrit
commit 989822c23cd0dc315c109aca4b24472ae503ece6
Author: David Imhoff <dimhoff_devel at xs4all.nl>
Date: Sun May 10 15:45:23 2015 +0200
intel/fsp_baytrail: Clarify naming of eMMC controllers
The first eMMC controller is a eMMC 4.41 controller. The second is a
eMMC 4.5 controller. Fix and extend define names and strings to indicate
which controller is ment.
TEST=Intel/MinnowMax
Change-Id: Ib341968898963c874e82be87fe85c0b6baea4748
Signed-off-by: David Imhoff <dimhoff_devel at xs4all.nl>
---
src/mainboard/intel/bayleybay_fsp/irqroute.h | 8 ++++----
src/mainboard/intel/minnowmax/devicetree.cb | 4 ++--
src/mainboard/intel/minnowmax/irqroute.h | 8 ++++----
src/mainboard/siemens/mc_tcu3/irqroute.h | 8 ++++----
src/soc/intel/fsp_baytrail/baytrail/pci_devs.h | 20 ++++++++++----------
src/soc/intel/fsp_baytrail/chip.h | 4 ++--
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 8 ++++----
src/soc/intel/fsp_baytrail/southcluster.c | 4 ++--
8 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h
index bce6f63..d36634a 100644
--- a/src/mainboard/intel/bayleybay_fsp/irqroute.h
+++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h
@@ -25,13 +25,13 @@
/*
*IR02h GFX INT(A) - PIRQ A
- *IR10h EMMC INT(ABCD) - PIRQ DEFG
+ *IR10h eMMC 4.41 INT(ABCD) - PIRQ DEFG
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
- *IR17h MMC INT(A) - PIRQ F
+ *IR17h eMMC 4.5 INT(A) - PIRQ F
*IR18h SIO INT(ABCD) - PIRQ BADC
*IR1Ah TXE INT(A) - PIRQ F
*IR1Bh HD Audio INT(A) - PIRQ G
@@ -50,13 +50,13 @@
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(EMMC441_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC45_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
index 6e456cb..645a89d 100644
--- a/src/mainboard/intel/minnowmax/devicetree.cb
+++ b/src/mainboard/intel/minnowmax/devicetree.cb
@@ -63,13 +63,13 @@ chip soc/intel/fsp_baytrail
device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
device pci 03.0 off end # 8086 0F38 - MIPI -
- device pci 10.0 off end # 8086 0F14 - EMMC Port -
+ device pci 10.0 off end # 8086 0F14 - eMMC 4.41 Port -
device pci 11.0 off end # 8086 0F15 - SDIO Port -
device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
- device pci 17.0 off end # 8086 0F50 - MMC Port -
+ device pci 17.0 off end # 8086 0F50 - eMMC 4.5 Port -
device pci 18.0 on end # 8086 0F40 - SIO - DMA -
device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h
index a4dce3b..d6960d4 100644
--- a/src/mainboard/intel/minnowmax/irqroute.h
+++ b/src/mainboard/intel/minnowmax/irqroute.h
@@ -26,13 +26,13 @@
/*
*IR02h GFX INT(A) - PIRQ A
- *IR10h EMMC INT(ABCD) - PIRQ DEFG
+ *IR10h eMMC 4.41 INT(ABCD) - PIRQ DEFG
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
- *IR17h MMC INT(A) - PIRQ F
+ *IR17h eMMC 4.5 INT(A) - PIRQ F
*IR18h SIO INT(ABCD) - PIRQ BADC
*IR1Ah TXE INT(A) - PIRQ F
*IR1Bh HD Audio INT(A) - PIRQ G
@@ -51,13 +51,13 @@
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(EMMC441_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC45_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h
index bce6f63..d36634a 100644
--- a/src/mainboard/siemens/mc_tcu3/irqroute.h
+++ b/src/mainboard/siemens/mc_tcu3/irqroute.h
@@ -25,13 +25,13 @@
/*
*IR02h GFX INT(A) - PIRQ A
- *IR10h EMMC INT(ABCD) - PIRQ DEFG
+ *IR10h eMMC 4.41 INT(ABCD) - PIRQ DEFG
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
- *IR17h MMC INT(A) - PIRQ F
+ *IR17h eMMC 4.5 INT(A) - PIRQ F
*IR18h SIO INT(ABCD) - PIRQ BADC
*IR1Ah TXE INT(A) - PIRQ F
*IR1Bh HD Audio INT(A) - PIRQ G
@@ -50,13 +50,13 @@
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(EMMC441_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC45_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
diff --git a/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h b/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h
index dc41d13..d02340b 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/pci_devs.h
@@ -47,11 +47,11 @@
# define MIPI_DEV_FUNC DEV_FUNC(MIPI_DEV,MIPI_FUNC)
-/* SDIO Port */
-#define EMMC_DEV 0x10
-#define EMMC_FUNC 0
-# define EMMC_DEVID 0x0f14
-# define EMMC_DEV_FUNC DEV_FUNC(EMMC_DEV,EMMC_FUNC)
+/* eMMC 4.41 Port */
+#define EMMC441_DEV 0x10
+#define EMMC441_FUNC 0
+# define EMMC441_DEVID 0x0f14
+# define EMMC441_DEV_FUNC DEV_FUNC(EMMC441_DEV,EMMC441_FUNC)
/* SDIO Port */
#define SDIO_DEV 0x11
@@ -106,11 +106,11 @@
# define OTG_DEVID 0x0f37
# define OTG_DEV_FUNC DEV_FUNC(LPE_DEV,LPE_FUNC)
-/* MMC Port */
-#define MMC45_DEV 0x17
-#define MMC45_FUNC 0
-# define MMC45_DEVID 0x0f50
-# define MMC45_DEV_FUNC DEV_FUNC(MMC45_DEV,MMC45_FUNC)
+/* eMMC 4.5 Port */
+#define EMMC45_DEV 0x17
+#define EMMC45_FUNC 0
+# define EMMC45_DEVID 0x0f50
+# define EMMC45_DEV_FUNC DEV_FUNC(EMMC45_DEV,EMMC45_FUNC)
/* Serial IO 1 */
#define SIO1_DEV 0x18
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 9a2edfe..d8438e0 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -71,14 +71,14 @@ struct soc_intel_fsp_baytrail_config {
*
* 0x0 "Disabled"
* 0x1 "Auto"
- * 0x2 "eMMC 4.1"
+ * 0x2 "eMMC 4.41"
* 0x3 "eMMC 4.5"
*/
uint8_t PcdeMMCBootMode;
#define EMMC_USE_DEFAULT UPD_DEFAULT
#define EMMC_DISABLED UPD_DISABLE
#define EMMC_AUTO INCREMENT_FOR_DEFAULT(1)
- #define EMMC_4_1 INCREMENT_FOR_DEFAULT(2)
+ #define EMMC_4_41 INCREMENT_FOR_DEFAULT(2)
#define EMMC_4_5 INCREMENT_FOR_DEFAULT(3)
#define EMMC_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index f7ca991..adfee6f 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -75,7 +75,7 @@ static const char *acpi_pci_mode_strings[] = {
static const char *emmc_mode_strings[] = {
"Disabled",
"Auto",
- "eMMC 4.1",
+ "eMMC 4.41",
"eMMC 4.5"
};
@@ -178,12 +178,12 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n",
dev->enabled?"Enabled":"Disabled");
break;
- case EMMC_DEV_FUNC: /* EMMC 4.1*/
+ case EMMC441_DEV_FUNC: /* eMMC 4.41 */
if ((dev->enabled) &&
(config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
- UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED;
+ UpdData->PcdeMMCBootMode = EMMC_4_41 - EMMC_DISABLED;
break;
- case MMC45_DEV_FUNC: /* MMC 4.5*/
+ case EMMC45_DEV_FUNC: /* eMMC 4.5 */
if ((dev->enabled) &&
(config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED;
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index d515286..352ab2b 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -511,9 +511,9 @@ static int place_device_in_d3hot(device_t dev)
switch (dev->path.pci.devfn) {
DEV_CASE(MIPI):
DEV_CASE(SDIO):
- DEV_CASE(EMMC):
+ DEV_CASE(EMMC441):
DEV_CASE(SD):
- DEV_CASE(MMC45):
+ DEV_CASE(EMMC45):
DEV_CASE(LPE):
DEV_CASE(SIO_DMA1):
DEV_CASE(I2C1):
More information about the coreboot-gerrit
mailing list