[coreboot-gerrit] Patch set updated for coreboot: 1ad3b8b tegra132: allow mainboards to insert memory regions in address map

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8925

-gerrit

commit 1ad3b8b06a7d8acd2ef0623e870c25dc7b6be554
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Aug 12 17:50:53 2014 -0500

    tegra132: allow mainboards to insert memory regions in address map
    
    Depending on the needs of the mainboard certain regions of the address
    map may need to be adjusted. Allow for that.
    
    BUG=chrome-os-partner:31293
    BRANCH=None
    TEST=With ryu patches able to insert a non-cacheable memory region.
    
    Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9
    Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/212161
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/soc/nvidia/tegra132/include/soc/addressmap.h |  8 ++++++
 src/soc/nvidia/tegra132/mmu_operations.c         | 31 ++++++++++++++----------
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h
index f5f72db..2a21c30 100644
--- a/src/soc/nvidia/tegra132/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h
@@ -100,6 +100,14 @@ enum {
 /* Provided the careout id, obtain the base and size in 1MiB units. */
 void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib);
 
+
+/*
+ * Add any board-specific memory ranges to the address map when executing
+ * on aarchv8 core.
+ */
+struct memranges;
+void mainboard_add_memory_ranges(struct memranges *map);
+
 /*
  * There are complications accessing the Trust Zone carveout region. The
  * AVP cannot access these registers and the CPU can't access this register
diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c
index 1514780..2c54d7f 100644
--- a/src/soc/nvidia/tegra132/mmu_operations.c
+++ b/src/soc/nvidia/tegra132/mmu_operations.c
@@ -44,39 +44,44 @@ static void print_memranges(struct memranges *mmap_ranges)
 
 }
 
-static void tegra132_memrange_init(void)
+static void tegra132_memrange_init(struct memranges *map)
 {
 	uint64_t start,end;
+	const unsigned long devmem = MA_DEV | MA_NS | MA_RW;
+	const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW;
 
-	memranges_init_empty(&t132_mmap_ranges);
+	memranges_init_empty(map);
 
 	memory_in_range_below_4gb(&start,&end);
 
 	/* Device memory below DRAM */
-	memranges_insert(&t132_mmap_ranges, 0, start * MiB, MA_DEV | MA_NS |
-			 MA_RW);
+	memranges_insert(map, 0, start * MiB, devmem);
 
 	/* DRAM */
-	memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
-			 MA_MEM | MA_NS | MA_RW);
+	memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem);
 
 	memory_in_range_above_4gb(&start,&end);
 
-	memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB,
-			 MA_MEM | MA_NS | MA_RW);
+	memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem);
 
 	/* SRAM */
-	memranges_insert(&t132_mmap_ranges, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE,
-			 MA_MEM | MA_NS | MA_RW);
+	memranges_insert(map, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, cachedmem);
+}
 
-	print_memranges(&t132_mmap_ranges);
+void __attribute__((weak)) mainboard_add_memory_ranges(struct memranges *map)
+{
+	/* Don't add any ranges by default. */
 }
 
 void tegra132_mmu_init(void)
 {
 	uint64_t *ttb_buffer = (uint64_t*)CONFIG_TTB_BUFFER;
 	uint64_t ttb_size = (uint64_t)CONFIG_TTB_SIZE;
-	tegra132_memrange_init();
-	mmu_init(&t132_mmap_ranges,ttb_buffer,ttb_size);
+	struct memranges *map = &t132_mmap_ranges;
+
+	tegra132_memrange_init(map);
+	mainboard_add_memory_ranges(map);
+	print_memranges(map);
+	mmu_init(map,ttb_buffer,ttb_size);
 	mmu_enable((uint64_t)ttb_buffer);
 }