[coreboot-gerrit] Patch set updated for coreboot: e40ca59 arm64: handle non-cacheable normal memory

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8924

-gerrit

commit e40ca5998d8ce07451edc301e633c4601a052bd6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Aug 12 17:40:38 2014 -0500

    arm64: handle non-cacheable normal memory
    
    Non-cacheable normal memory is needed when one wants an easy way
    to have a DMA region. That way all the reads and writes will be
    picked up by the CPU and the device without any cache management
    operations.
    
    BUG=chrome-os-partner:31293
    BRANCH=None
    TEST=With a bevy of other patches can use a carved out DMA region
         for talking to USB.
    
    Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6
    Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/212160
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
 src/arch/arm64/armv8/mmu.c              | 12 ++++++++++--
 src/arch/arm64/include/armv8/arch/mmu.h |  3 +++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index e1f088e..cba1e4d 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -67,8 +67,16 @@ static uint64_t get_block_attr(unsigned long tag)
 	attr = (tag & MA_NS)? BLOCK_NS : 0;
 	attr |= (tag & MA_RO)? BLOCK_AP_RO : BLOCK_AP_RW;
 	attr |= BLOCK_ACCESS;
-	attr |= (tag & MA_MEM)? (BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT) :
-		(BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT);
+
+	if (tag & MA_MEM) {
+		if (tag & MA_MEM_NC)
+			attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT;
+		else
+			attr |= BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT;
+	} else {
+		attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT;
+	}
+
 
 	return attr;
 }
diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h
index f5f60a1..7639bd5 100644
--- a/src/arch/arm64/include/armv8/arch/mmu.h
+++ b/src/arch/arm64/include/armv8/arch/mmu.h
@@ -47,6 +47,9 @@
 #define MA_RO                      (1 << 2)
 #define MA_RW                      (0 << 2)
 
+/* Non-cacheable memory. */
+#define MA_MEM_NC                  (1 << 3)
+
 /* Descriptor attributes */
 
 #define INVALID_DESC               0x0