[coreboot-gerrit] New patch to review for coreboot: a359cdd samus: Updates for EVT board
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Tue Mar 24 21:36:07 CET 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8963
-gerrit
commit a359cdd56c6b8f72e27ae074418233e51503cba0
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Fri Aug 22 13:36:12 2014 -0700
samus: Updates for EVT board
- Remove NFC GPIOs
- Change EC wake to GPIO27
- Enable wake on HOTWORD_DET_L_3V3
- Add new Hynix memory SKU
BUG=chrome-os-partner:31549
BRANCH=none
TEST=emerge-samus coreboot, cannot fully test until EVT
Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213796
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
(cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1
---
src/mainboard/google/samus/acpi/mainboard.asl | 28 ++++++++++++++++++++---
src/mainboard/google/samus/devicetree.cb | 3 +++
src/mainboard/google/samus/gpio.h | 10 ++++----
src/mainboard/google/samus/spd/Makefile.inc | 2 +-
src/mainboard/google/samus/spd/hynix_16Gb.spd.hex | 18 +++++++++++++++
5 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 8d5ecc6..45a0c64 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -27,9 +27,8 @@ Scope (\_SB)
Return (\_SB.PCI0.LPCB.EC0.LIDS)
}
- // There is no GPIO for LID, the EC pulses WAKE# pin instead.
- // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
- Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
+ // EC wake is GPIO27 which is a special DeepSX wake pin
+ Name (_PRW, Package(){ 0x70, 5 }) // GP27_EN
}
Device (PWRB)
@@ -189,6 +188,29 @@ Scope (\_SB.PCI0.I2C0)
}
}
}
+
+ Device (HOTW)
+ {
+ Name (_HID, "PNP0A05")
+ Name (_DDN, "Hotword Wake")
+ Name (_UID, 1)
+ Name (GPIO, 46) /* HOTWORD_DET_L_3V3 */
+
+ Name (_PRW, Package() { GPIO, 3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
+ }
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+ }
}
Scope (\_SB.PCI0.I2C1)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 95ab44b..4bbc3af 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -45,6 +45,9 @@ chip soc/intel/broadwell
register "sata_port_map" = "0x1"
register "sio_acpi_mode" = "1"
+ # Set I2C0 to 1.8V
+ register "sio_i2c0_voltage" = "1"
+
# Force enable ASPM for PCIe Port 3
register "pcie_port_force_aspm" = "0x04"
register "pcie_port_coalesce" = "1"
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
index 806804c..b7ddcb0 100644
--- a/src/mainboard/google/samus/gpio.h
+++ b/src/mainboard/google/samus/gpio.h
@@ -35,7 +35,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
- PCH_GPIO_PIRQ, /* 9: NFC_INT (PIRQ) */
+ PCH_GPIO_UNUSED, /* 9: UNUSED */
PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
PCH_GPIO_UNUSED, /* 11: UNUSED */
PCH_GPIO_UNUSED, /* 12: UNUSED */
@@ -52,8 +52,8 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */
PCH_GPIO_UNUSED, /* 24: UNUSED */
PCH_GPIO_INPUT, /* 25: EC_IN_RW */
- PCH_GPIO_OUT_HIGH, /* 26: NFC_EN */
- PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 26: UNUSED */
+ PCH_GPIO_ACPI_SCI, /* 27: PCH_WAKE_L */
PCH_GPIO_UNUSED, /* 28: UNUSED */
PCH_GPIO_UNUSED, /* 29: UNUSED */
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
@@ -72,7 +72,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
PCH_GPIO_UNUSED, /* 44: UNUSED */
PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */
- PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */
+ PCH_GPIO_ACPI_SCI, /* 46: HOTWORD_DET_L_3V3 (WAKE) */
PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */
PCH_GPIO_UNUSED, /* 48: UNUSED */
PCH_GPIO_UNUSED, /* 49: UNUSED */
@@ -90,7 +90,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
+ PCH_GPIO_UNUSED, /* 64: UNUSED */
PCH_GPIO_INPUT, /* 65: RAM_ID3 */
PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */
PCH_GPIO_INPUT, /* 67: RAM_ID0 */
diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc
index 774ea57..4d5257e 100644
--- a/src/mainboard/google/samus/spd/Makefile.inc
+++ b/src/mainboard/google/samus/spd/Makefile.inc
@@ -35,7 +35,7 @@ SPD_SOURCES += empty # 0b1001
SPD_SOURCES += samsung_8Gb # 0b1010
SPD_SOURCES += empty # 0b1011
SPD_SOURCES += hynix_8Gb # 0b1100
-SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += hynix_16Gb # 0b1101
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111
diff --git a/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex
new file mode 100644
index 0000000..55db8dc
--- /dev/null
+++ b/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex
@@ -0,0 +1,18 @@
+# Hynix H9CNNNNCLTMLAR-NTM LPDDR3
+# banks 8, ranks 2, rows 15, columns 11, density 16384 Mb, x32
+91 20 F1 03 06 1A 05 0B 03 11 01 08 0A 00 50 01
+78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
+00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
+54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
More information about the coreboot-gerrit
mailing list