[coreboot-gerrit] Patch merged into coreboot/master: d08057a intel/fsp_baytrail: Add PCI Root Port IRQ Routing

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d08057aa20d8dff404ba9121a5d2052ae6575356
Author: Martin Roth <gaumless at gmail.com>
Date:   Thu Feb 12 22:51:57 2015 -0700

    intel/fsp_baytrail: Add PCI Root Port IRQ Routing
    
    This change generates the ASL tables needed for the PCIe bridge routing.
    
    It generates this ASL (swizzled for each of the 8 functions)
    Name(RP1P, Package()
    {
    	Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
    	Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
    	Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
    	Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
    })
    Name(RP1A, Package()
    {
    	Package() {0x0000ffff, 0, 0, 20 },
    	Package() {0x0000ffff, 1, 0, 21 },
    	Package() {0x0000ffff, 2, 0, 22 },
    	Package() {0x0000ffff, 3, 0, 23 },
    })
    Device(RP01) {
    	Name(_ADR, 0x1c0001)
    	Name(_PRW, Package() {
    		0, 0
    	})
    	Method(_PRT,0) {
    		If(PICM) {
    			Return (RP1A)
    		} Else {
    			Return (RP1P)
    		}
    	}
    }
    
    Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30
    Signed-off-by: Martin Roth <gaumless at gmail.com>
    Reviewed-on: http://review.coreboot.org/8429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/8429 for details.

-gerrit