[coreboot-gerrit] Patch set updated for coreboot: 1ba3469 northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP

[Alexander Couzens (lynxis@fe80.eu)]

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8659

-gerrit

commit 1ba3469eb4267d6e64d1aaf635a8e9b495a42caa
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Feb 26 01:30:40 2015 +0100

    northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
    
    This capability means:
    FERR messages are sent out on system detected an
    unmasked floating point x87 FPU error.
    
    Even though this capability is supported on nehalem it doesn't
    make sense to set it in early stage. This MSR
    has a core scope which results in an unsync MSR because
    it's not set on other cores than the BSP.
    
    Found-by: BITS
    Tested-on: lenovo thinkpad x201t
    
    Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/northbridge/intel/nehalem/early_init.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 56c0d68..9c9d1b4 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -131,11 +131,6 @@ static void early_cpu_init (void)
 	m = rdmsr(MSR_IA32_MISC_ENABLES);
 	m.lo |= 0x10000;
 	wrmsr(MSR_IA32_MISC_ENABLES, m);
-
-	m = rdmsr(0x1f1);
-	m.lo |= 1;
-	wrmsr(0x1f1, m);
-
 }
 
 void nehalem_early_initialization(int chipset_type)