[coreboot-gerrit] Patch merged into coreboot/master: ddr3: Fix SPD CRC calculation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 8c639359ea6dcb0eb445a37c1c276652b34ff437
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Mon Jun 22 19:32:53 2015 +0200

    ddr3: Fix SPD CRC calculation
    
    Use the correct SPD size for crc calculation. sizeof(*spd) returns 4
    while sizeof(spd_raw_data) returns the expected value of 256.
    Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log.
    Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H.
    
    Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
    Reviewed-on: http://review.coreboot.org/10629
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nicolas Reinecke <nr at das-labor.org>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/10629 for details.

-gerrit