[coreboot-gerrit] Patch merged into coreboot/master: AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 6762a8b85e631c9076990021ac2392c5efcbda21
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Mon Jun 8 10:13:13 2015 +0800

    AMD PI agesawrapper: add PSPP (PCIe Speed Power Policy) interface
    
    PSPP policy is defined in 3rdparty/blobs/pi/amd/*/AGESA.h
    /// PCIe PSPP Power policy
    typedef enum  {
      PsppDisabled,                                           ///< PSPP disabled
      PsppPerformance = 1,                                    ///< Performance
      PsppBalanceHigh,                                        ///< Balance-High
      PsppBalanceLow,                                         ///< Balance-Low
      PsppPowerSaving,                                        ///< Power Saving
      MaxPspp                                                 ///< Max Pspp for boundary check
    } PCIE_PSPP_POLICY;
    
    Change-Id: I7fe735cddea94a83e38d856a3de1f27735467a28
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Reviewed-on: http://review.coreboot.org/10461
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/10461 for details.

-gerrit