[coreboot-gerrit] Patch set updated for coreboot: lippert/toucan-af: 64bit fixes

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Sat Jun 20 20:27:58 CEST 2015


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10599

-gerrit

commit 7cef7a56ed108651497ba56146cf8419d671fac1
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Fri Jun 19 15:55:01 2015 -0700

    lippert/toucan-af: 64bit fixes
    
    Change-Id: I9e7f78587b9d6e87cf77757654da9145d4187625
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/mainboard/lippert/toucan-af/mainboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index d46fbc8..4afef23 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -93,7 +93,7 @@ static void init(struct device *dev)
 	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
 
 	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
-	spi_base = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
+	spi_base = (u8*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
 	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
 
 	/* Notify the SMC we're alive and kicking, or after a while it will



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