[coreboot-gerrit] Patch set updated for coreboot: 9da565a sandy/ivy: Fix PIRQs on Chromebooks

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Sat Jun 6 10:53:19 CEST 2015


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9993

-gerrit

commit 9da565a10bcd80a750a5170bd20cedc40f56cbcb
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 6 11:52:24 2015 +0300

    sandy/ivy: Fix PIRQs on Chromebooks
    
    This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
    internal USB EHCI controller broken, with no assigned IRQ.
    
    PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
    for the GPIO to use. They cannot be used for PCI devices at the same time.
    
    Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 .../google/butterfly/acpi/sandybridge_pci_irqs.asl | 64 +++++++++++++++++++
 src/mainboard/google/butterfly/dsdt.asl            |  2 +-
 src/mainboard/google/butterfly/romstage.c          | 42 ++++++++++++-
 .../google/link/acpi/sandybridge_pci_irqs.asl      | 68 ++++++++++++++++++++
 src/mainboard/google/link/dsdt.asl                 |  2 +-
 src/mainboard/google/link/romstage.c               | 39 +++++++++++-
 .../google/parrot/acpi/sandybridge_pci_irqs.asl    | 68 ++++++++++++++++++++
 src/mainboard/google/parrot/dsdt.asl               |  2 +-
 src/mainboard/google/parrot/romstage.c             | 43 ++++++++++++-
 .../google/stout/acpi/sandybridge_pci_irqs.asl     | 72 ++++++++++++++++++++++
 src/mainboard/google/stout/dsdt.asl                |  2 +-
 src/mainboard/google/stout/romstage.c              | 43 ++++++++++++-
 .../samsung/lumpy/acpi/sandybridge_pci_irqs.asl    | 68 ++++++++++++++++++++
 src/mainboard/samsung/lumpy/dsdt.asl               |  2 +-
 src/mainboard/samsung/lumpy/romstage.c             | 36 ++++++++++-
 .../samsung/stumpy/acpi/sandybridge_pci_irqs.asl   | 68 ++++++++++++++++++++
 src/mainboard/samsung/stumpy/dsdt.asl              |  2 +-
 src/mainboard/samsung/stumpy/romstage.c            | 38 +++++++++++-
 18 files changed, 649 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..f2afacd
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
+			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
+			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
+			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/google/butterfly/dsdt.asl
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index b25492d..f73e6bc 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -60,7 +60,47 @@ void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P2IP  ETH0   INTB -> PIRQF
+	 * D28IP_P3IP  SDCARD INTC -> PIRQD
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQF
+	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+	 *
+	 * Trackpad interrupt is edge triggered and cannot be shared.
+	 * TRACKPAD                -> PIRQG
+
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+			(INTC << D28IP_P3IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..2c2e1ec
--- /dev/null
+++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
index a01533f..1b35193 100644
--- a/src/mainboard/google/link/dsdt.asl
+++ b/src/mainboard/google/link/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index e9b4a09..505e25c 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -76,7 +76,44 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P3IP  WLAN   INTA -> PIRQB
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQF
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+	 *
+	 * TRACKPAD                -> PIRQE (Edge Triggered)
+	 * TOUCHSCREEN             -> PIRQG (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P3IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..2c2e1ec
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/google/parrot/dsdt.asl
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index a947c48..b073fe7 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -60,7 +60,48 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P2IP  WLAN   INTA -> PIRQB
+	 * D28IP_P3IP  ETH0   INTC -> PIRQD
+	 * D29IP_E1P   EHCI1  INTA -> PIRQE
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * Trackpad DVT PIRQA (16)
+	 * Trackpad DVT PIRQE (20)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+		(INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+		(NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
+		(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..3fe7a46
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// XHCI	0:14.0
+			Package() { 0x0014ffff, 0, 0, 19 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// XHCI   0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
index 01e4001..c7ab62d 100644
--- a/src/mainboard/google/stout/dsdt.asl
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 31b61e2..43ac459 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -66,7 +66,48 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX         INTA -> PIRQA (MSI)
+	 * D20IP_XHCI  XHCI        INTA -> PIRQD (MSI)
+	 * D26IP_E2P   EHCI #2     INTA -> PIRQF
+	 * D27IP_ZIP   HDA         INTA -> PIRQA (MSI)
+	 * D28IP_P2IP  WLAN        INTA -> PIRQD
+	 * D28IP_P3IP  Card Reader INTB -> PIRQE
+	 * D28IP_P6IP  LAN         INTC -> PIRQB
+	 * D29IP_E1P   EHCI #1     INTA -> PIRQD
+	 * D31IP_SIP   SATA        INTA -> PIRQB (MSI)
+	 * D31IP_SMIP  SMBUS       INTB -> PIRQH
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+		(INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+		(NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
+		(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+	RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
+	DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..3762372
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 16 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 17 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 17 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 1ab6322..107e1aa 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -50,7 +50,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 015ae08..e067da0 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -72,7 +72,41 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQB
+	 * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
+	 * D31IP_SMIP  SMBUS  INTC -> PIRQH
+	 * D31IP_TTIP  THRT   INTB -> PIRQG
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * LIGHTSENSOR             -> PIRQE (Edge Triggered)
+	 * TRACKPAD                -> PIRQF (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
 	RCBA16(OIC) = 0x0100;
diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..7d692b9
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 0a2f37d..365f89a 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -48,7 +48,7 @@ DefinitionBlock(
 		{
 			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-			#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+			#include "acpi/sandybridge_pci_irqs.asl"
 		}
 	}
 
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 161c8d1..fc0a2e9 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -84,7 +84,43 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	southbridge_configure_default_intmap();
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);



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