[coreboot-gerrit] Patch merged into coreboot/master: skylake: Update microcode reload in ramstage.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a7ff45309020118cb88fae98ffe9da5c856f83e2
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Jul 23 22:40:53 2015 +0530

    skylake: Update microcode reload in ramstage.
    
    For Skylake, Microcode is being loaded from FIT, Skylake supports
    the PRMRR/SGX feature. If This is supported the FIT microcode
    load will set the msr (0x08b) with the Patch id one less than the
    id in the microcode binary. This results in Microcode getting
    reloaded again in bootclock and ramstage (MP init).
    Avoid the microcode reload by checking for PRMRR support.
    
    BUG=chrome-os-partner:42046
    BRANCH=None TEST=Built for glados and tested on RVP3
    CQ-DEPEND=CL:287513
    
    Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a
    Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/287674
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11056
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11056 for details.

-gerrit