[coreboot-gerrit] Patch merged into coreboot/master: kunimitsu: Update Serial IO modes in devicetree

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 75154b801f8c31298125d4fc0a3ee069058dc0b6
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date:   Thu Jul 9 18:00:40 2015 +0530

    kunimitsu: Update Serial IO modes in devicetree
    
    This patch updates the Serial IO modes for UART 1 and 2
    in devicetree for kunimitsu boards.
    UART1 are disabled and
    UART2 is in PCI mode.
    
    BRANCH=None
    BUG=chrome-os-partner:40857
    TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu.
    
    Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627
    Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a
    Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284825
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Reviewed-on: http://review.coreboot.org/11001
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11001 for details.

-gerrit