[coreboot-gerrit] Patch merged into coreboot/master: Sklrvp: Update Serial IO modes in devicetree

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit baf4e3e92d02f9a1976acf4efcd4baec86c56c49
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date:   Thu Jul 9 17:59:58 2015 +0530

    Sklrvp: Update Serial IO modes in devicetree
    
    This patch updates the Serial IO modes for UART 1 and 2
    in devicetree for sklrvp boards.
    UART1 is disabled and
    UART2 is in PCI mode.
    
    BRANCH=None
    BUG=chrome-os-partner:40857
    TEST=Built for sklrvp and tested LPSS logs on RVP3.
    
    Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da
    Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56
    Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284824
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Reviewed-on: http://review.coreboot.org/11000
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/11000 for details.

-gerrit