[coreboot-gerrit] Patch merged into coreboot/master: Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f077de66ffdbbd191f09ae8a4d6f08d0313be90f
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date:   Mon Jul 6 16:42:56 2015 +0530

    Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol
    
    This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1
    substate for PCIe.
    
    BRANCH=None
    BUG=chrome-os-partner:42331
    TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows
    "L1 enabled and LTR enabled"
    
    Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83
    Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4
    Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/284775
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Reviewed-on: http://review.coreboot.org/10988
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/10988 for details.

-gerrit