[coreboot-gerrit] Patch merged into coreboot/master: skylake: honor pcie root port settings already in chip.h

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 02b3243dd39291425c325a1e2df6618c5a45d934
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Jul 13 14:03:41 2015 -0500

    skylake: honor pcie root port settings already in chip.h
    
    For some unkonwn reason the pcie root port settings weren't
    being honored in the device tree. Fix that omission.
    
    BUG=chrome-os-partner:41861
    BRANCH=None
    TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
         settings were being honored.
    
    Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
    Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/285027
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/10987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/10987 for details.

-gerrit