[coreboot-gerrit] New patch to review for coreboot: amd8111, ck804, mcp55: use CONFIG_HPET_ADDRESS

[Jonathan A. Kollasch (jakllsch@kollasch.net)]

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10925

-gerrit

commit 1a75a61584ad2f9e27934c140915e2b7d527d35c
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jul 15 13:47:33 2015 -0500

    amd8111, ck804, mcp55: use CONFIG_HPET_ADDRESS
    
    As acpi_write_hpet() uses CONFIG_HPET_ADDRESS in the HPET table we
    need to use CONFIG_HPET_ADDRESS when assigning it to the device.
    
    Change-Id: I656f917658f1c1717bb3653fa048a6d36fca2454
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/amd/amd8111/lpc.c  | 2 +-
 src/southbridge/nvidia/ck804/lpc.c | 2 +-
 src/southbridge/nvidia/mcp55/lpc.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index df3eff4..8841760 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -26,7 +26,7 @@ static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
 
-	pci_write_config32(dev,0xa0, 0xfed00001);
+	pci_write_config32(dev, 0xa0, CONFIG_HPET_ADDRESS|1);
 	hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
 	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
 
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index d0f687f..be8a39c 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -207,7 +207,7 @@ static void ck804_lpc_read_resources(device_t dev)
 
 		res = find_resource(dev, 0x44); /* HPET */
 		if (res) {
-			res->base = 0xfed00000;
+			res->base = CONFIG_HPET_ADDRESS;
 			res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 		}
 	}
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 8d1a83a..5726c76 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -83,7 +83,7 @@ static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
 
-	pci_write_config32(dev, 0x44, 0xfed00001);
+	pci_write_config32(dev, 0x44, CONFIG_HPET_ADDRESS|1);
 	hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe;
 	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
 }