[coreboot-gerrit] New patch to review for coreboot: 85be05c mainboard: Sanitize some superio include paths to be non-local
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sat Jan 3 18:27:09 CET 2015
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8052
-gerrit
commit 85be05cb4ba48eebc5c7cd0e5643fc6d9e490d74
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sun Jan 4 04:17:35 2015 +1100
mainboard: Sanitize some superio include paths to be non-local
This brings mainboard up to being consistent tree-wide now for
all superio header path inclusions.
Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/intel/cougar_canyon2/romstage.c | 2 +-
src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
src/mainboard/intel/mtarvon/romstage.c | 2 +-
src/mainboard/intel/truxton/romstage.c | 2 +-
src/mainboard/lenovo/t60/dock.c | 2 +-
src/mainboard/lenovo/x60/dock.c | 2 +-
src/mainboard/samsung/lumpy/romstage.c | 2 +-
src/mainboard/samsung/stumpy/romstage.c | 2 +-
src/mainboard/supermicro/h8qgi/romstage.c | 2 +-
src/mainboard/supermicro/h8scm/romstage.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 6580ab9..7194851 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -33,7 +33,7 @@
#include <console/console.h>
#include <halt.h>
#include <reset.h>
-#include "superio/smsc/sio1007/chip.h"
+#include <superio/smsc/sio1007/chip.h>
#include <fsp_util.h>
#include "northbridge/intel/fsp_sandybridge/northbridge.h"
#include "northbridge/intel/fsp_sandybridge/raminit.h"
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 76edf7f..ffb44a0 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -30,7 +30,7 @@
#include <arch/acpi.h>
#include <cbmem.h>
#include <console/console.h>
-#include "superio/smsc/sio1007/chip.h"
+#include <superio/smsc/sio1007/chip.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index c1ee9bb..4691b5c 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -29,7 +29,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
-#include "superio/intel/i3100/i3100.h"
+#include <superio/intel/i3100/i3100.h>
#include "superio/intel/i3100/early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 0677cf6..f750778 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -30,7 +30,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
-#include "superio/intel/i3100/i3100.h"
+#include <superio/intel/i3100/i3100.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/intel/i3100/early_serial.c"
#include "lib/debug.c" // XXX
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index b01f8e8..8052dbc 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -24,7 +24,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
-#include "superio/nsc/pc87384/pc87384.h"
+#include <superio/nsc/pc87384/pc87384.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c
index 1f85281..1a843d9 100644
--- a/src/mainboard/lenovo/x60/dock.c
+++ b/src/mainboard/lenovo/x60/dock.c
@@ -26,7 +26,7 @@
#include <arch/io.h>
#include "dock.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
-#include "superio/nsc/pc87392/pc87392.h"
+#include <superio/nsc/pc87392/pc87392.h>
static void dlpc_write_register(int reg, int value)
{
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 5b8646a..b356fa8 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -44,7 +44,7 @@
#include "option_table.h"
#include "gpio.h"
#if CONFIG_DRIVERS_UART_8250IO
-#include "superio/smsc/lpc47n207/lpc47n207.h"
+#include <superio/smsc/lpc47n207/lpc47n207.h>
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
#if CONFIG_CHROMEOS
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index f842ad2..1462132 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -44,7 +44,7 @@
#include <halt.h>
#include "gpio.h"
#if CONFIG_DRIVERS_UART_8250IO
-#include "superio/smsc/lpc47n207/lpc47n207.h"
+#include <superio/smsc/lpc47n207/lpc47n207.h>
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
#if CONFIG_CHROMEOS
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 477f1c4..c231e31 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -31,7 +31,7 @@
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
-#include "superio/nuvoton/wpcm450/wpcm450.h"
+#include <superio/nuvoton/wpcm450/wpcm450.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 6e7ad70..0bbd8bc 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -31,7 +31,7 @@
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
-#include "superio/nuvoton/wpcm450/wpcm450.h"
+#include <superio/nuvoton/wpcm450/wpcm450.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index fdf49d8..917e9e3 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -46,7 +46,7 @@
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/sr5650/sr5650.h"
-#include "superio/nuvoton/wpcm450/wpcm450.h"
+#include <superio/nuvoton/wpcm450/wpcm450.h>
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
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