[coreboot-gerrit] New patch to review for coreboot: c584067 libpayload: provide icache_invalidate_all() on ARM64

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9903

-gerrit

commit c58406783f121c41c226360dd86444e69ff0f2cd
Author: Furquan Shaikh <furquan at google.com>
Date:   Tue Mar 31 22:50:17 2015 -0700

    libpayload: provide icache_invalidate_all() on ARM64
    
    In order to not duplicate the instruction cache invalidation
    sequence provide a common routine to perform the necessary
    actions. Also, use it in the appropriate places.
    
    BUG=chrome-os-partner:38231
    BRANCH=None
    TEST=Compiles successfully for smaug and boots kernel
    
    Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529
    Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/263326
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
---
 payloads/libpayload/arch/arm64/cache.c         |  4 +---
 payloads/libpayload/include/arm64/arch/cache.h | 11 +++++++++++
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c
index 2ce1cc4..799e2d2 100644
--- a/payloads/libpayload/arch/arm64/cache.c
+++ b/payloads/libpayload/arch/arm64/cache.c
@@ -120,7 +120,5 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
 void cache_sync_instructions(void)
 {
 	dcache_clean_all();	/* includes trailing DSB (in assembly) */
-	iciallu();		/* includes BPIALLU (architecturally) */
-	dsb();
-	isb();
+	icache_invalidate_all(); /* includes leading DSB and trailing ISB */
 }
diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h
index cfd3109..7577758 100644
--- a/payloads/libpayload/include/arm64/arch/cache.h
+++ b/payloads/libpayload/include/arm64/arch/cache.h
@@ -103,6 +103,17 @@ void cache_sync_instructions(void);
 /* tlb invalidate all */
 void tlb_invalidate_all(void);
 
+/* Invalidate all of the instruction cache for PE to PoU. */
+static inline void icache_invalidate_all(void)
+{
+	__asm__ __volatile__(
+		"dsb	sy\n\t"
+		"ic	iallu\n\t"
+		"dsb	sy\n\t"
+		"isb\n\t"
+	: : : "memory");
+}
+
 /*
  * Generalized setup/init functions
  */