[coreboot-gerrit] Patch merged into coreboot/master: 59074ff pistachio: clean DDR2 initialization code

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 59074ff89fee709a3822d50a400834b70dd87b23
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Thu Mar 5 16:40:07 2015 +0000

    pistachio: clean DDR2 initialization code
    
    The proper way to initialize DDR2 is for the PHY to
    automatically establish precise timing configuration
    through the training process. The alternative (used
    initially for testing) is no longer needed.
    
    This change determined the removal of some local
    variables as they ended up being used in one location only.
    
    BUG=chrome-os-partner:31438, chrome-os-partner:37087
    TEST=tested on Pistachio bring up board -> DDR initialized
         properly and ramstage executed correctly.
    BRANCH=none
    
    Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd
    Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/256303
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/9845
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9845 for details.

-gerrit