[coreboot-gerrit] New patch to review for coreboot: 3d43682 libpayload: mips: Do not set C0_EBase_WG

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9822

-gerrit

commit 3d436820842230cc1d8e3fe11ebdf33ffd4132b2
Author: Andrew Bresticker <abrestic at chromium.org>
Date:   Thu Feb 5 13:51:50 2015 -0800

    libpayload: mips: Do not set C0_EBase_WG
    
    The WG (write gate) bit in C0_EBase allows the upper two bits of
    the exception base address to be set to something other than 2'b10,
    thus allowing it to be relocated out of the traditional KSEG{0,1}
    range.  Since we're not using the segmentation features introduced
    by EVA to relocate the unmapped segments, the exception vectors
    should remain in KSEG0.  Don't set the WG bit so that the upper
    two bits of the exception base (2'b00, because of the identity
    mapping) are ignored and we execute the exception vectors out of
    KSEG0.
    
    BUG=chrome-os-partner:36258
    BRANCH=none
    TEST=Build and boot on Pistachio.
    
    Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea
    Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d
    Original-Signed-off-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/246697
    Original-Reviewed-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
---
 payloads/libpayload/arch/mips/exception_asm.S | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/payloads/libpayload/arch/mips/exception_asm.S b/payloads/libpayload/arch/mips/exception_asm.S
index 5906d39..85386ac 100644
--- a/payloads/libpayload/arch/mips/exception_asm.S
+++ b/payloads/libpayload/arch/mips/exception_asm.S
@@ -20,7 +20,6 @@
 #define	STATUS_REGISTER		$12,0
 #define	BOOT_EXC_VECTOR_MASK	(1 << 22)
 #define	EBASE_REGISTER		$15,1
-#define	WRITE_GATE_MASK		(1 << 11)
 #define	EXCEPTION_BASE_MASK	(0xFFFFF000)
 
 	/* Don't reorder instructions */
@@ -192,9 +191,6 @@ exception_init_asm:
 	and	$t0, $t0, $t2
 	/* Filling base address */
 	or	$t0, $t0, $t1
-	/* Setting WG bit */
-	li	$t2, WRITE_GATE_MASK
-	or	$t0, $t0, $t2
 	mtc0	$t0, EBASE_REGISTER
 
 	/* Clear boot exception vector bit for EBASE value to take effect */