[coreboot-gerrit] Patch merged into coreboot/master: 7271e23 pistachio: report UART register width

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7271e23ec296b09420b72861e0d272ecbb94d2ca
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Jan 9 16:55:36 2015 -0800

    pistachio: report UART register width
    
    Pistachio UART closely matches 8250, the only difference is that its
    register file is mapped to a 32 bit bus.
    
    Provide a function to report register with so that the Coreboot table
    entry gets correct value.
    
    BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=with the rest of the patches integrated depthcharge console messages
         show up when running on the FPGA board
    
    Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087
    Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/240028
    Original-Reviewed-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9740 for details.

-gerrit