[coreboot-gerrit] Patch merged into coreboot/master: 6cc5e52 libpayload: read register width from coreboot table

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 6cc5e52ec66585682d251f32f901c4db7b51b4d4
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Jan 9 16:54:19 2015 -0800

    libpayload: read register width from coreboot table
    
    Some SOCs (like pistachio, for instance) provide an 8250 compatible
    UART, which has the same register layout, but mapped to a bus of a
    different width.
    
    Instead of adding a new driver for these controllers, it is better to
    have coreboot report UART register width to libpayload, and have it
    adjust the offsets accordingly when accessing the UART.
    
    BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=with the rest of the patches integrated depthcharge console messages
         show up when running on the FPGA board
    
    Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
    Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/240027
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9739 for details.

-gerrit