[coreboot-gerrit] New patch to review for coreboot: 1537918 fsp platforms: consolidate FspNotify calls
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Fri Apr 17 05:21:48 CEST 2015
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9780
-gerrit
commit 1537918f9857c940e372a4c780bdaccb8d0ee535
Author: Martin Roth <gaumless at gmail.com>
Date: Thu Apr 16 21:20:34 2015 -0600
fsp platforms: consolidate FspNotify calls
Consolidate the FspNotify calls into the FSP driver directory,
using BOOT_STATE_INIT_ENTRY to set up the call times.
Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
src/drivers/intel/fsp/fsp_util.c | 29 ++++++++++++++++++++++
src/northbridge/intel/fsp_rangeley/northbridge.c | 22 ----------------
.../intel/fsp_sandybridge/northbridge.c | 23 -----------------
src/soc/intel/fsp_baytrail/chip.c | 20 ---------------
4 files changed, 29 insertions(+), 65 deletions(-)
diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c
index a00cb81..45b65a2 100644
--- a/src/drivers/intel/fsp/fsp_util.c
+++ b/src/drivers/intel/fsp/fsp_util.c
@@ -317,6 +317,35 @@ static void find_fsp_hob_update_mrc(void *unused)
}
}
+/** @brief Notify FSP for PostPciEnumeration.
+ *
+ * @param unused
+ */
+static void fsp_after_pci_enum(void *unused)
+{
+ /* This call needs to be done before resource allocation. */
+ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
+ FspNotify(EnumInitPhaseAfterPciEnumeration);
+ printk(BIOS_DEBUG,
+ "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
+}
+
+/** @brief Notify FSP for ReadyToBoot
+ *
+ * @param unused
+ */
+static void fsp_finalize(void *unused)
+{
+ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
+ print_fsp_info();
+ FspNotify(EnumInitPhaseReadyToBoot);
+ printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
+}
+
+/* Set up for the ramstage FSP calls */
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
+
/* Update the MRC/fast boot cache as part of the late table writing stage */
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
find_fsp_hob_update_mrc, NULL);
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index be3a3ac..59fdfa3 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -112,17 +112,6 @@ static int add_fixed_resources(struct device *dev, int index)
return index;
}
-static void finalize_dev (device_t dev)
-{
- /*
- * Notify FSP for PostPciEnumeration.
- * Northbridge APIC init should be early and late enough...
- */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
- FspNotify(EnumInitPhaseAfterPciEnumeration);
- printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
-}
-
static void mc_add_dram_resources(device_t dev)
{
u32 tomlow, bmbound, bsmmrrl, bsmmrrh;
@@ -233,7 +222,6 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
- .final = finalize_dev,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
@@ -294,17 +282,7 @@ static void enable_dev(device_t dev)
}
}
-static void finalize_chip(void *chip_info)
-{
- /* Notify FSP for ReadyToBoot */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
- print_fsp_info();
- FspNotify(EnumInitPhaseReadyToBoot);
- printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
-}
-
struct chip_operations northbridge_intel_fsp_rangeley_ops = {
CHIP_NAME("Intel Rangeley Northbridge")
.enable_dev = enable_dev,
- .final = finalize_chip,
};
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index fac635d..17e7723 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -39,7 +39,6 @@
#include <fsp_util.h>
static int bridge_revision_id = -1;
-static u8 finished_FSP_after_pci = 0;
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
@@ -372,31 +371,9 @@ static void enable_dev(device_t dev)
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
-
- /*
- * Notify FSP for PostPciEnumeration.
- * This call needs to be done before resource allocation.
- */
- if (!finished_FSP_after_pci) {
- finished_FSP_after_pci = 1;
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
- FspNotify(EnumInitPhaseAfterPciEnumeration);
- printk(BIOS_DEBUG,
- "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n\n");
- }
-}
-
-static void finalize_chip(void *chip_info)
-{
- /* Notify FSP for ReadyToBoot */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
- print_fsp_info();
- FspNotify(EnumInitPhaseReadyToBoot);
- printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
}
struct chip_operations northbridge_intel_fsp_sandybridge_ops = {
CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")
.enable_dev = enable_dev,
- .final = finalize_chip,
};
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
index 732d1dc..3024ede 100644
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ b/src/soc/intel/fsp_baytrail/chip.c
@@ -30,22 +30,11 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
-static void finalize_dev (device_t dev)
-{
- /*
- * Notify FSP for PostPciEnumeration.
- * Northbridge APIC init should be early and late enough...
- */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
- FspNotify(EnumInitPhaseAfterPciEnumeration);
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
- .final = &finalize_dev,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
@@ -77,14 +66,6 @@ static void enable_dev(device_t dev)
}
}
-static void finalize_chip(void *chip_info)
-{
- /* Notify FSP for ReadyToBoot */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
- FspNotify(EnumInitPhaseReadyToBoot);
-
-}
-
/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
static void soc_init(void *chip_info)
{
@@ -95,7 +76,6 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
CHIP_NAME("Intel BayTrail SoC")
.enable_dev = enable_dev,
.init = soc_init,
- .final = &finalize_chip,
};
static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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