[coreboot-gerrit] New patch to review for coreboot: f97e48c rk3288: Handle framebuffer through memlayout, not the resource system
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Apr 16 11:54:58 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9732
-gerrit
commit f97e48ceac50283cb47b70ab171c890920388768
Author: Julius Werner <jwerner at chromium.org>
Date: Wed Jan 14 14:53:59 2015 -0800
rk3288: Handle framebuffer through memlayout, not the resource system
We've traditionally tucked the framebuffer at the end of memory (above
CBMEM) on ARM and declared it reserved through coreboot's resource
allocator. This causes depthcharge to mark this area as reserved in the
kernel's device tree, which may be necessary to avoid display corruption
on handoff but also wastes space that the OS could use instead.
Since rk3288 boards now have proper display shutdown code in
depthcharge, keeping the framebuffer memory reserved across the handoff
(and thus throughout the lifetime of the system) should no longer be
necessary. For now let's just switch the rk3288 implementation to define
it through memlayout instead, which is not communicated through the
coreboot tables and will get treated as normal memory by depthcharge.
Note that this causes it to get wiped in developer/recovery mode, which
should not be a problem because that is done in response to VbInit()
(long before any images are drawn) and 0 is the default value for a
corebootfb anyway (a black pixel).
Eventually, we might want to think about adding more memory types to
coreboot's resource system (e.g. "reserved until kernel handoff", or
something specifically for the frame buffer) to model this situation
better, and maybe merge it with memlayout somehow.
CQ-DEPEND=CL:239470
BRANCH=veyron
BUG=chrome-os-partner:34713
TEST=Booted Jerry, noticed that 'free' now displays 0x7f000 more bytes
than before (curiously not 0x80000 bytes, I guess there's some alignment
waste in the kernel somewhere). Made sure the memory map output from
coreboot looks as expected, there's no visible display corruption in
developer/recovery mode and the 'cbmem' utility still works.
Change-Id: I12b7bfc1b7525f5a08cb7c64f0ff1b174df252d4
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 10afdba54dd5d680acec9cb3fe5b9234e33ca5a2
Original-Change-Id: I1950407d3b734e2845ef31bcef7bc59b96c2ea03
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240819
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/arch/arm/include/arch/memlayout.h | 11 +++++++++--
src/include/symbols.h | 4 ++++
src/soc/rockchip/rk3288/cbmem.c | 4 ++--
src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 +
src/soc/rockchip/rk3288/include/soc/soc.h | 8 --------
src/soc/rockchip/rk3288/soc.c | 12 +++++-------
6 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h
index 2c73394..1cba7bd 100644
--- a/src/arch/arm/include/arch/memlayout.h
+++ b/src/arch/arm/include/arch/memlayout.h
@@ -22,6 +22,8 @@
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
+#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M)
+
#define TTB(addr, size) \
REGION(ttb, addr, size, 16K) \
_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
@@ -36,8 +38,13 @@
#define STACK(addr, size) REGION(stack, addr, size, 8)
#define DMA_COHERENT(addr, size) \
- REGION(dma_coherent, addr, size, (1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) \
- _ = ASSERT(size % ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) == 0, \
+ REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \
+ _ = ASSERT(size % SUPERPAGE_SIZE == 0, \
"DMA coherency buffer must fit exactly in full superpages!");
+#define FRAMEBUFFER(addr, size) \
+ REGION(framebuffer, addr, size, SUPERPAGE_SIZE) \
+ _ = ASSERT(size % SUPERPAGE_SIZE == 0, \
+ "Framebuffer must fit exactly in full superpages!");
+
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 2259dcb..c3ced87 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -77,4 +77,8 @@ extern u8 _dma_coherent[];
extern u8 _edma_coherent[];
#define _dma_coherent_size (_edma_coherent - _dma_coherent)
+extern u8 _framebuffer[];
+extern u8 _eframebuffer[];
+#define _framebuffer_size (_eframebuffer - _framebuffer)
+
#endif /* __SYMBOLS_H */
diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c
index 1c3a902..2eed972 100644
--- a/src/soc/rockchip/rk3288/cbmem.c
+++ b/src/soc/rockchip/rk3288/cbmem.c
@@ -18,11 +18,11 @@
*/
#include <cbmem.h>
-#include <soc/soc.h>
#include <stddef.h>
+#include <symbols.h>
void *cbmem_top(void)
{
- return (void *)(get_fb_base_kb()*KiB);
+ return _dram + (size_t)CONFIG_DRAM_SIZE_MB*MiB;
}
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 7a8b77c..f5d3ca8 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -31,6 +31,7 @@ SECTIONS
RAMSTAGE(0x00200000, 128K)
POSTRAM_CBFS_CACHE(0x01000000, 1M)
DMA_COHERENT(0x10000000, 2M)
+ FRAMEBUFFER(0x10800000, 8M)
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
diff --git a/src/soc/rockchip/rk3288/include/soc/soc.h b/src/soc/rockchip/rk3288/include/soc/soc.h
index c6ab7f4..05f54da 100644
--- a/src/soc/rockchip/rk3288/include/soc/soc.h
+++ b/src/soc/rockchip/rk3288/include/soc/soc.h
@@ -27,12 +27,4 @@
#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
-#define FB_SIZE_KB 8192
-#define RAM_BASE_KB ((uintptr_t)_dram >> 10)
-#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
-
-static inline u32 get_fb_base_kb(void)
-{
- return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
-}
#endif
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index abd93d7..fa26c6d 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -28,30 +28,28 @@
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
static void soc_init(device_t dev)
{
- unsigned long fb_size = FB_SIZE_KB * KiB;
- u32 lcdbase = get_fb_base_kb() * KiB;
-
- ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
- mmio_resource(dev, 1, lcdbase / KiB, fb_size / KiB);
+ ram_resource(dev, 0, (uintptr_t)_dram/KiB,
+ CONFIG_DRAM_SIZE_MB*(MiB/KiB));
if (vboot_skip_display_init())
printk(BIOS_INFO, "Skipping display init.\n");
#if !IS_ENABLED(CONFIG_SKIP_DISPLAY_INIT_HACK)
else
- rk_display_init(dev, lcdbase, fb_size);
+ rk_display_init(dev, (uintptr_t)_framebuffer,
+ _framebuffer_size);
#endif
}
static struct device_operations soc_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
.init = soc_init,
.scan_bus = 0,
};
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