[coreboot-gerrit] Patch merged into coreboot/master: 129b5fa rk3288: Fix failing LPDDR3 reboot test

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 129b5fa973ca4d2c5e2a62bede3470da3bf8de3b
Author: jinkun.hong <jinkun.hong at rock-chips.com>
Date:   Wed Jan 21 15:47:25 2015 +0800

    rk3288: Fix failing LPDDR3 reboot test
    
    tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate
    this signal, but the max value we can set is 7, so the standard can not be met.
    So, now we send the Mode Register Set command manually, and hence we can add
    the delay manually.
    
    BUG=chrome-os-partner:34608
    TEST=loop reboot
    BRANCH=veyron
    
    Change-Id: Id974ab935c2df6ea35dcdd240378ffc68de0204d
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: b60a4de6ff3ad3720c2c06ed7de03ed942360e6c
    Original-Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d
    Original-Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/242176
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/9654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9654 for details.

-gerrit