[coreboot-gerrit] Patch merged into coreboot/master: d4a227b rk3288: Fix failing DDR3 reboot test

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d4a227ba05aadf049cec0b4e4edc8345f476c2f4
Author: jinkun.hong <jinkun.hong at rock-chips.com>
Date:   Wed Jan 21 16:03:43 2015 +0800

    rk3288: Fix failing DDR3 reboot test
    
    We want a reset signal to last 200us. The length of a reset signal is
    represented by BIT0~BIT16 in DDR_PUBL_PTR2. When DDR memory runs at
    667MHz, the calculated value for the reset signal is 0x20850, which is
    bigger than the maximum value that can be described with 17 bits
    (0x1ffff). As a result, the memory controller only sees 0x850, which
    generates a 3.5us reset cycle instead, which violates the standard and
    negatively impacts memory stability.
    So instead, we now set it to the maximum value (0x1ffff) to prevent this
    overflow, resulting in a reset signal of 196us for 667MHz DDR memory.
    
    BUG=chrome-os-partner:34875
    TEST=loop reboot
    BRANCH=veyron
    
    Change-Id: Ia01f8a0414b49fa3ecf4d543cfa1822e29ee4cc4
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 767a4a3cb8dff47cb15064d335b78ffa5815914d
    Original-Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f
    Original-Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/242175
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: http://review.coreboot.org/9653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9653 for details.

-gerrit