[coreboot-gerrit] New patch to review for coreboot: d42cbb8 urara: Reduce MIPS PLL jitter

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9671

-gerrit

commit d42cbb8b7052ae030bdfe8212f55fdea556cb32a
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Tue Feb 3 00:26:08 2015 +0000

    urara: Reduce MIPS PLL jitter
    
    The current MIPS PLL is configured in such a way that there is
    excessive jitter.  Correct this by applying new PLL settings. The
    resultant frequency is 546MHz instead of 550MHz.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board as part of the JTAG
         loading script;
    BRANCH=none
    
    Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0
    Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/245620
    Original-Reviewed-by: James Hartley <james.hartley at imgtec.com>
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
---
 src/mainboard/google/urara/bootblock.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c
index b21a888..f8f62f7 100644
--- a/src/mainboard/google/urara/bootblock.c
+++ b/src/mainboard/google/urara/bootblock.c
@@ -111,7 +111,7 @@ static int init_clocks(void)
 	/* The same frequency will be the input frequency for the SPFI block */
 	system_clk_setup(1);
 
-	/* MIPS CPU dividers: division by 1 -> 550 MHz
+	/* MIPS CPU dividers: division by 1 -> 546 MHz
 	 * This is set up as we cannot make any assumption about
 	 * the values set or not by the boot ROM code */
 	mips_clk_setup(0, 0);
@@ -135,8 +135,8 @@ static int init_clocks(void)
 	ret = sys_pll_setup(2, 1);
 	if (ret != CLOCKS_OK)
 		return ret;
-	/* Setup MIPS PLL at 550 MHz */
-	ret = mips_pll_setup(2, 1, 13, 275);
+	/* Setup MIPS PLL at 546 MHz */
+	ret = mips_pll_setup(2, 1, 1, 21);
 	if (ret != CLOCKS_OK)
 		return ret;
 	return CLOCKS_OK;