[coreboot-gerrit] New patch to review for coreboot: 046310b pistachio: Fix ROM clock base address

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9670

-gerrit

commit 046310b9ff27073fc5a0a72ae1427c0f748b5e51
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Mon Feb 2 14:34:24 2015 +0000

    pistachio: Fix ROM clock base address
    
    The base address used was TOP CLOCK control address instead of
    the PERIPH CLOCK CONTROL. That was incorrect and is fixed with
    the current patch.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board; now the hash accelerator,
         fed by this clock, is correctly clocked at 200MHz.
    BRANCH=none
    
    Change-Id: I0ead3951dc1dfc872881b8d1ae9b63f8104af50d
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 871cb50ca43a6c760f346eb447e8ff102d8ca0b6
    Original-Change-Id: I198d64f97a85a6fcf00c3853bf23d2d767e0e631
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/245313
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/imgtec/pistachio/clocks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index d50abf5..5b22640 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -99,7 +99,7 @@
 #define UART1CLKOUT_MASK		0x000003FF
 
 /* Definitions for ROM clock setup */
-#define ROMCLKOUT_CTRL_ADDR		0xB814410C
+#define ROMCLKOUT_CTRL_ADDR		0xB814490C
 #define ROMCLKOUT_MASK			0x0000007F
 
 /* Definitions for ETH clock setup */