[coreboot-gerrit] Patch merged into coreboot/master: e244986 rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e244986e40f0e3b9e08b2156bcc45f6fc18976d2
Author: Julius Werner <jwerner at chromium.org>
Date:   Mon Oct 20 18:04:29 2014 -0700

    rk3288: Increase PD_BUS_ACLK (SRAM clock) to improve boot speed
    
    This patch doubles the ACLK peripheral clock for the PD_BUS power domain
    to 297MHz, which is the closest to the maximum of 300MHz we can reach by
    dividing GPLL. This frequency directly translates into SRAM speed, so
    maximizing it has a huge impact on boot speed (especially with the lack
    of SRAM caching).
    
    BUG=chrome-os-partner:32987
    TEST=Booted Veyron_Pinky. Hacked timestamps into vboot and confirmed
    that the (visibly) long signature verification times are nearly halved.
    
    Change-Id: Iafa3044854a4058a7f885c775119d964a6295de4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c230585f4344d0eab4f8eeaa761869965f2da08a
    Original-Change-Id: I3f19eaa3d97dcc6235d820c71eb5edf2ae87d647
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/224524
    Original-Trybot-Ready: Doug Anderson <dianders at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/9600
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9600 for details.

-gerrit