[coreboot-gerrit] New patch to review for coreboot: 3b0c416 tpm: wait for valid bit to be set in TPM access register before using tpm

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9567

-gerrit

commit 3b0c41698ce40877c93767a93c31cb9f695b358d
Author: Sourabh Banerjee <sbanerje at codeaurora.org>
Date:   Tue Jan 20 15:18:40 2015 +0530

    tpm: wait for valid bit to be set in TPM access register before using tpm
    
    As per the TCG PC Client TPM Interface Specification v1.2, bit 7 of the
    access register (tmpRegValiSts bit) stays "0" until the TPM has complete
    through self test and initialization. This bit is set "1" to indicate that
    the other bits in the register are valid.
    
    BRANCH=chromeos-2013.04
    BUG=chrome-os-partner:35328
    TEST=Booted up storm p0.2 and whirwind sp3.
    Verified TPM chip is detected and reported in coreboot logs.
    
    Change-Id: I1049139fc155bfd2e1f29e3b8a7b9d2da6360857
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 006fc93c6308d6f3fa220f00708708aa62cc676c
    Original-Change-Id: I9df3388ee1ef6e4a9d200d99aea1838963747ecf
    Original-Signed-off-by: Sourabh Banerjee <sbanerje at codeaurora.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/242222
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
---
 src/drivers/i2c/tpm/tis.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index 696634d..d9a7651 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -29,6 +29,7 @@
 #include <device/i2c.h>
 #include <tpm.h>
 #include "tpm.h"
+#include <timer.h>
 
 #include <console/console.h>
 
@@ -37,6 +38,7 @@ struct tpm_chip g_chip;
 
 #define TPM_CMD_COUNT_BYTE 2
 #define TPM_CMD_ORDINAL_BYTE 6
+#define TPM_VALID_STATUS (1 << 7)
 
 int tis_open(void)
 {
@@ -74,12 +76,33 @@ int tis_init(void)
 {
 	int bus = CONFIG_DRIVER_TPM_I2C_BUS;
 	int chip = CONFIG_DRIVER_TPM_I2C_ADDR;
+	struct stopwatch sw;
+	uint8_t buf = 0;
+	int ret;
+	long sw_run_duration = 750;
 
 	/*
-	 * Probe TPM twice; the first probing might fail because TPM is asleep,
-	 * and the probing can wake up TPM.
+	 * Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1)
+	 * If the bit remains clear(0) then claim that init has failed.
 	 */
-	if (i2c_writeb(bus, chip, 0, 0) && i2c_writeb(bus, chip, 0, 0))
+	stopwatch_init_msecs_expire(&sw, sw_run_duration);
+	do {
+		ret = i2c_readb(bus, chip, 0, &buf);
+		if (!ret && (buf & TPM_VALID_STATUS)) {
+			sw_run_duration = stopwatch_duration_msecs(&sw);
+			break;
+		}
+	} while (!stopwatch_expired(&sw));
+
+	printk(BIOS_INFO,
+	       "%s: ValidSts bit %s(%d) in TPM_ACCESS register after %ld ms\n",
+	       __func__, (buf & TPM_VALID_STATUS) ? "set" : "clear",
+	       (buf & TPM_VALID_STATUS) >> 7, sw_run_duration);
+
+	/*
+	 * Claim failure if the ValidSts (bit 7) is clear.
+	 */
+	if (!(buf & TPM_VALID_STATUS))
 		return -1;
 
 	return 0;