[coreboot-gerrit] Patch merged into coreboot/master: 5c8d43e baytrail: fix the coding error on PCIe L1 exit latency

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5c8d43e207b4349e95ffb359e0ed08ffa3f789a0
Author: Kevin L Lee <kevin.l.lee at intel.com>
Date:   Fri Dec 12 14:02:43 2014 +0800

    baytrail: fix the coding error on PCIe L1 exit latency
    
    The original code uses L1EXIT_MASK to shift the bit for
    PCIe L1 exit latency, the code should use L1EXIT_SHIFT
    for bit shifting.
    
    BUG=chrome-os-partner:34037
    BRANCH=None
    TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
    set to 010b. Correspond WIFI device performance got improvement.
    Signed-off-by: Kevin L Lee <kevin.l.lee at intel.com>
    
    Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
    Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
    Original-Reviewed-on: https://chromium-review.googlesource.com/234673
    Original-Reviewed-by: Kenji Chen <kenji.chen at intel.com>
    Original-Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Original-Tested-by: Kenji Chen <kenji.chen at intel.com>
    Original-Commit-Queue: Kenji Chen <kenji.chen at intel.com>
    Reviewed-on: http://review.coreboot.org/9480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9480 for details.

-gerrit