[coreboot-gerrit] New patch to review for coreboot: fb9249c tegra132: Add framebuffer parameters

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9520

-gerrit

commit fb9249c406d5bccb139567c9e4ea635b7dcc1be9
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Fri Nov 14 20:44:40 2014 -0800

    tegra132: Add framebuffer parameters
    
    Framebuffer line size and number of lines can have different
    values than panel's resolution.
    
    BRANCH=none
    BUG=chrome-os-partner:31936
    TEST=build and test on ryu
    
    Change-Id: I228f1dd7fafc6577a8e8a987ff31ba73f7a655ed
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9a4929dc5831076f2f2a5dd2e13f24b3477e197b
    Original-Change-Id: Iedeef796f02286bb03920413420f8952cf34334a
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/229915
    Original-Tested-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/nvidia/tegra132/chip.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h
index 35e72d5..2468870 100644
--- a/src/soc/nvidia/tegra132/chip.h
+++ b/src/soc/nvidia/tegra132/chip.h
@@ -27,7 +27,8 @@ struct soc_nvidia_tegra132_config {
 	uintptr_t spintable_addr;
 
 	/*
-	 * panel default specification
+	 * panel resolution
+	 *  The two parameters below provides dc about panel spec.
 	 */
 	u32 xres;		/* the width of H display active area */
 	u32 yres;		/* the height of V display active area */
@@ -45,6 +46,15 @@ struct soc_nvidia_tegra132_config {
 	 */
 	u32 framebuffer_size;
 
+	/*
+	 * Framebuffer resolution
+	 *  The two parameters below provides dc about framebuffer's sdram size.
+	 *  When they are not the same as panel resolution, we need to program
+	 *  dc's DDA_INCREMENT and some other registers to resize dc output.
+	 */
+	u32 display_xres;
+	u32 display_yres;
+
 	int href_to_sync;	/* HSYNC position with respect to line start */
 	int hsync_width;	/* the width of HSYNC pulses */
 	int hback_porch;	/* the distance between HSYNC trailing edge to