[coreboot-gerrit] New patch to review for coreboot: f93a7fc cubieboard: Initialize memory in bootblock

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4630

-gerrit

commit f93a7fc6c21479b7a72619bdcc7b032c340929e8
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Tue Dec 31 00:57:30 2013 -0500

    cubieboard: Initialize memory in bootblock
    
    Even though the Allwinner A10 is limited to a 24KiB bootblock, the
    memory initialization takes only about 3KiB and leaves enough room for
    an MMC or NAND driver, so init the memory early on. The advantage is
    that we can eliminate complicated logistics of where to cache CBFS and
    where to load the ramstage in SRAM.
    
    Change-Id: Id549552ed509434e831db60deaef28e04d62417f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/cpu/allwinner/a10/Makefile.inc             |  2 ++
 src/mainboard/cubietech/cubieboard/bootblock.c | 42 ++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc
index 8e743a2..3e7b535 100644
--- a/src/cpu/allwinner/a10/Makefile.inc
+++ b/src/cpu/allwinner/a10/Makefile.inc
@@ -1,6 +1,8 @@
 bootblock-y	+= clock.c
+bootblock-y	+= raminit.c
 bootblock-y	+= gpio.c
 bootblock-y	+= pinmux.c
+bootblock-y	+= timer.c
 bootblock-y	+= bootblock_media.c
 bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
 bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c
diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c
index 8899160..2e5929c 100644
--- a/src/mainboard/cubietech/cubieboard/bootblock.c
+++ b/src/mainboard/cubietech/cubieboard/bootblock.c
@@ -9,8 +9,10 @@
 #include <arch/io.h>
 #include <uart.h>
 #include <console/console.h>
+#include <delay.h>
 #include <cpu/allwinner/a10/gpio.h>
 #include <cpu/allwinner/a10/clock.h>
+#include <cpu/allwinner/a10/dramc.h>
 
 #define CPU_AHB_APB0_DEFAULT 		\
 	 CPU_CLK_SRC_OSC24M	 	\
@@ -76,10 +78,50 @@ static void cubieboard_enable_uart(void)
 	a1x_periph_clock_enable(A1X_CLKEN_UART0);
 }
 
+static void cubieboard_raminit(void)
+{
+	struct dram_para dram_para = {
+		.clock = 480,
+		.type = 3,
+		.rank_num = 1,
+		.density = 4096,
+		.io_width = 16,
+		.bus_width = 32,
+		.cas = 6,
+		.zq = 123,
+		.odt_en = 0,
+		.size = 1024,
+		.tpr0 = 0x30926692,
+		.tpr1 = 0x1090,
+		.tpr2 = 0x1a0c8,
+		.tpr3 = 0,
+		.tpr4 = 0,
+		.tpr5 = 0,
+		.emr1 = 0,
+		.emr2 = 0,
+		.emr3 = 0,
+	};
+
+	dramc_init(&dram_para);
+
+	/* FIXME: ram_check does not compile for ARM,
+	 * and we didn't init console yet
+	 */
+	////void *const test_base = (void *)A1X_DRAM_BASE;
+	////ram_check((u32)test_base, (u32)test_base + 0x1000);
+}
+
 void bootblock_mainboard_init(void);
 void bootblock_mainboard_init(void)
 {
+	/* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very
+	 * early on to get udelay, which is used almost everywhere else.
+	 */
+	init_timer();
+
 	cubieboard_setup_clocks();
 	cubieboard_setup_gpios();
 	cubieboard_enable_uart();
+
+	cubieboard_raminit();
 }