[coreboot-gerrit] New patch to review for coreboot: 1e06657 northbridge/intel/*/acpi/igd.asl: Trivial indent style fix
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sat Dec 6 04:33:23 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7665
-gerrit
commit 1e06657010505546803456b26083143d08c329eb
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Dec 6 14:32:23 2014 +1100
northbridge/intel/*/acpi/igd.asl: Trivial indent style fix
Change-Id: I26e92645264c69bbc032b0e7e44d7d31de2dfa4d
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/northbridge/intel/gm45/acpi/igd.asl | 4 ++--
src/northbridge/intel/nehalem/acpi/igd.asl | 22 +++++++++++-----------
src/northbridge/intel/sandybridge/acpi/igd.asl | 4 ++--
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
index c5b4b6a..199765b 100644
--- a/src/northbridge/intel/gm45/acpi/igd.asl
+++ b/src/northbridge/intel/gm45/acpi/igd.asl
@@ -27,8 +27,8 @@ Device (GFX0)
Field (GFXC, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
- BAR0, 64
- }
+ BAR0, 64
+ }
OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl
index a892ce2..8c6c174 100644
--- a/src/northbridge/intel/nehalem/acpi/igd.asl
+++ b/src/northbridge/intel/nehalem/acpi/igd.asl
@@ -24,21 +24,21 @@ Device (GFX0)
Name (_ADR, 0x00020000)
OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
- Field (GFXC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x10),
- BAR0, 64
- }
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
- OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
- {
- Offset (0x48254),
+ {
+ Offset (0x48254),
BCLV, 16,
- Offset (0xc8250),
- CR1, 32,
+ Offset (0xc8250),
+ CR1, 32,
CR2, 32
- }
+ }
/* Display Output Switching */
Method (_DOS, 1)
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index d40fad5..8c6c174 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -27,10 +27,10 @@ Device (GFX0)
Field (GFXC, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
- BAR0, 64
+ BAR0, 64
}
- OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
{
Offset (0x48254),
More information about the coreboot-gerrit
mailing list